Semiconductor device, method for manufacturing the same, or display device including the same

ABSTRACT

A gate electrode, a first insulating film thereover, an oxide semiconductor film thereover, a source electrode and a drain electrode thereover, and a second insulating film thereover are included. The source and the drain electrodes each include a first conductive film, a second conductive film over and in contact with the first conductive film, and a third conductive film over and in contact with the second conductive film. The second conductive film includes copper. The first and the third conductive films each include an oxide conductive film. An end portion of the first conductive film includes a region located outward from an end portion of the second conductive film. The third conductive film covers a top surface and a side surface of the second conductive film and includes a region in contact with the first conductive film.

BACKGROUND OF THE INVENTION

1. Field of the Invention

One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. Another embodiment of the present invention relates to a manufacturing method of the semiconductor device including an oxide semiconductor film.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, manufacture, and a composition of matter. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof, and a manufacturing method thereof.

In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are each an embodiment of a semiconductor device. An imaging device, a display device, a liquid crystal display device, a light-emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like), and an electronic device may each include a semiconductor device.

2. Description of the Related Art

Attention has been focused on a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface (also referred to as a field-effect transistor (FET) or a thin film transistor (TFT)). Such a transistor is applied to a wide range of electronic devices such as an integrated circuit (IC) or an image display device (display device). A semiconductor material typified by silicon is widely known as a material for a semiconductor thin film that can be used for a transistor. As another material, an oxide semiconductor has been attracting attention.

For example, a transistor whose active layer includes an amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn) and having an electron carrier concentration of lower than 1×10¹⁸/cm³ is disclosed (see Patent Document 1).

REFERENCE Patent Document

[Patent Document 1] Japanese Published Patent Application No. 2006-165528

SUMMARY OF THE INVENTION

Reducing the resistance of a wiring, as well as increasing the mobility of a transistor, is effective in increasing the integration degree of an integrated circuit and miniaturizing an image display device. As a material for a wiring in a semiconductor device, copper has been examined. In the case of using a copper wiring, a barrier layer that prevents copper in the copper wiring from diffusing into a semiconductor film is required in order not to impair the transistor characteristics. The barrier layer can also prevent diffusion of impurities into the copper wiring and a reduction in the conductivity of the copper wiring.

In a transistor using an oxide semiconductor film for a channel region, oxygen vacancy which is formed in the oxide semiconductor film adversely affects the transistor characteristics. For example, oxygen vacancy formed in the oxide semiconductor film is bonded with hydrogen to serve as a carrier supply source. The carrier supply source generated in the oxide semiconductor film causes a change in the electrical characteristics, typically, shift in the threshold voltage, of the transistor including the oxide semiconductor film. Thus, it is necessary to reduce oxygen vacancy by effectively supplying oxygen to the channel region of the oxide semiconductor film.

Furthermore, in the case where a carrier supply source is generated near a source and a drain in a channel formed of an oxide semiconductor film, effective channel lengths are shortened or varied. The carrier supply source is formed with oxygen vacancy and hydrogen; therefore, it is particularly necessary to prevent oxygen diffusion from the oxide semiconductor film to the source and the drain.

In view of the foregoing problems, an object of one embodiment of the present invention is to suppress a change in electrical characteristics and to improve reliability in a transistor including an oxide semiconductor film. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a novel display device.

Note that the description of the above object does not disturb the existence of other objects. In one embodiment of the present invention, there is no need to achieve all the objects. Objects other than the above objects will be apparent from and can be derived from the description of the specification and the like.

A semiconductor device of one embodiment of the present invention includes a gate electrode, a first insulating film thereover, an oxide semiconductor film thereover, a source electrode and a drain electrode thereover, and a second insulating film thereover. The source electrode and the drain electrode each include a first conductive film, a second conductive film over and in contact with the first conductive film, and a third conductive film over and in contact with the second conductive film. The second conductive film includes copper. The first conductive film and the third conductive film are each a metal oxide. An end portion of the first conductive film includes a region located outward from an end portion of the second conductive film. The third conductive film covers a top surface and a side surface of the second conductive film and includes a region in contact with the first conductive film.

In the above-described embodiment, it is preferable that a fourth conductive film be provided over and in contact with the second insulating film, the fourth conductive film include an oxide conductive film, an opening portion be included in the second insulating film, and the fourth conductive film be electrically connected to the third conductive film through the opening portion.

In the above-described embodiment, it is preferable that the first conductive film and the third conductive film be oxides including indium, tin, zinc, and one or more selected independently from tungsten, molybdenum, and titanium. These are metal oxides having conductivity, and a film including the metal oxide is also referred to as oxide conductive film in this specification.

In the above embodiment, it is preferable that the oxide semiconductor film include In, M (M is Al, Ga, Y, or Sn), and Zn. In the above embodiment, it is preferable that the oxide semiconductor film include a crystal part and the crystal part have c-axis alignment.

Another embodiment of the present invention is a display device including the semiconductor device according to any one of the above embodiments, and a display element. Another embodiment of the present invention is a display module including the display device and a touch sensor. Another embodiment of the present invention is an electronic device including the semiconductor device according to any one of the above embodiments, the display device, or the display module, and an operation key or a battery.

In a transistor including an oxide semiconductor film of one embodiment of the present invention, a change in electrical characteristics can be suppressed and reliability can be improved. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a novel display device can be provided.

Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily achieve all the effects listed above. Other effects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C are a top view and cross-sectional views illustrating one embodiment of a semiconductor device.

FIGS. 2A and 2B are cross-sectional views illustrating one embodiment of a semiconductor device.

FIGS. 3A and 3B are cross-sectional views illustrating one embodiment of a semiconductor device.

FIGS. 4A and 4B are cross-sectional views illustrating one embodiment of a semiconductor device.

FIGS. 5A and 5B are cross-sectional views illustrating one embodiment of a semiconductor device.

FIGS. 6A and 6B are cross-sectional views illustrating one embodiment of a semiconductor device.

FIGS. 7A to 7C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device.

FIGS. 8A to 8C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device.

FIGS. 9A to 9C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device.

FIG. 10 is a cross-sectional view illustrating an example of a manufacturing process of a semiconductor device.

FIGS. 11A to 11C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device.

FIG. 12 is a cross-sectional view illustrating an example of a manufacturing process of a semiconductor device.

FIGS. 13A to 13C each illustrate an atomic ratio range of an oxide semiconductor.

FIG. 14 illustrates a crystal of InMZnO₄.

FIGS. 15A and 15B are each a band diagram of a stacked-layer structure of oxide semiconductors.

FIGS. 16A to 16E show structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD and selected-area electron diffraction patterns of a CAAC-OS.

FIGS. 17A to 17E show a cross-sectional TEM image and plan-view TEM images of a CAAC-OS and images obtained through analysis thereof.

FIGS. 18A to 18D show electron diffraction patterns and a cross-sectional TEM image of an nc-OS.

FIGS. 19A and 19B show cross-sectional TEM images of an a-like OS.

FIG. 20 shows a change in the crystal part of an In—Ga—Zn oxide induced by electron irradiation.

FIG. 21 is a top view illustrating one embodiment of a display device.

FIG. 22 is a cross-sectional view illustrating one embodiment of a display device.

FIG. 23 is a cross-sectional view illustrating one embodiment of a display device.

FIG. 24 is a cross-sectional view illustrating one embodiment of a display device.

FIG. 25 is a cross-sectional view illustrating one embodiment of a display device.

FIG. 26 is a cross-sectional view illustrating one embodiment of a display device.

FIG. 27 is a cross-sectional view illustrating one embodiment of a display device.

FIGS. 28A to 28C are a block diagram and circuit diagrams illustrating a display device.

FIGS. 29A to 29C are circuit diagrams and a timing chart illustrating one embodiment of the present invention.

FIGS. 30A to 30C are a graph and circuit diagrams illustrating one embodiment of the present invention.

FIGS. 31A and 31B are a circuit diagram and a timing chart illustrating one embodiment of the present invention.

FIGS. 32A and 32B are a circuit diagram and a timing chart illustrating one embodiment of the present invention.

FIGS. 33A to 33E are a block diagram, circuit diagrams, and waveform diagrams illustrating one embodiment of the present invention.

FIGS. 34A and 34B are a circuit diagram and a timing chart illustrating one embodiment of the present invention.

FIGS. 35A and 35B are circuit diagrams each illustrating one embodiment of the present invention.

FIGS. 36A to 36C are circuit diagrams each illustrating one embodiment of the present invention.

FIG. 37 illustrates a display module.

FIGS. 38A to 38E illustrate electronic devices.

FIGS. 39A to 39G illustrate electronic devices.

FIGS. 40A and 40B are perspective views illustrating a display device.

FIGS. 41A and 41B show etching rates of films.

FIGS. 42A to 42E show TDS measurement results of films.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments will be described with reference to drawings. However, the embodiments can be implemented in many different modes, and it will be readily appreciated by those skilled in the art that modes and details thereof can be changed in various ways without departing from the spirit and scope of the present invention. Thus, the present invention should not be interpreted as being limited to the following description of the embodiments.

In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, embodiments of the present invention are not limited to such a scale. Note that the drawings are schematic views showing ideal examples, and embodiments of the present invention are not limited to shapes or values shown in the drawings.

Note that in this specification, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components, and the terms do not limit the components numerically.

Note that in this specification, terms for describing arrangement, such as “over” “above”, “under”, and “below”, are used for convenience in describing a positional relation between components with reference to drawings. Further, the positional relation between components is changed as appropriate in accordance with a direction in which the components are described. Thus, the positional relation is not limited to that described with a term used in this specification and can be explained with another term as appropriate depending on the situation.

In this specification and the like, a transistor is an element having at least three terminals of a gate, a drain, and a source. In addition, the transistor has a channel region between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow between the source and the drain through the channel region. Note that in this specification and the like, a channel region refers to a region through which current mainly flows.

Further, functions of a source and a drain might be switched when transistors having different polarities are employed or a direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be switched in this specification and the like.

Note that in this specification and the like, the expression “electrically connected” includes the case where components are connected through an “object having any electric function”. There is no particular limitation on an “object having any electric function” as long as electric signals can be transmitted and received between components that are connected through the object. Examples of an “object having any electric function” are a switching element such as a transistor, a resistor, an inductor, a capacitor, and elements with a variety of functions as well as an electrode and a wiring.

In this specification and the like, the term “parallel” means that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also covers the case where the angle is greater than or equal to −5° and less than or equal to 5°. The term “perpendicular” means that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also covers the case where the angle is greater than or equal to 85° and less than or equal to 95°.

In this specification and the like, the terms “film” and “layer” can be interchanged with each other. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. Also, the term “insulating film” can be changed into the term “insulating layer” in some cases.

In this specification and the like, a metal oxide means an oxide of metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also simply referred to as an OS), and the like. For example, a metal oxide used in an active layer of a transistor is called an oxide semiconductor in some cases. In other words, an OS FET is a transistor including a metal oxide or an oxide semiconductor.

In this specification and the like, a metal oxide including nitrogen is also called a metal oxide in some cases. Moreover, a metal oxide including nitrogen may be called a metal oxynitride.

In this specification and the like, “c-axis aligned crystal (CAAC)” or “cloud-aligned composite (CAC)” might be stated. CAAC refers to an example of a crystal structure, and CAC refers to an example of a function or a material composition.

An example of a crystal structure of an oxide semiconductor or a metal oxide is described. Note that an oxide semiconductor deposited by a sputtering method using an In—Ga—Zn oxide target (In:Ga:Zn=4:2:4.1 in an atomic ratio) is described below as an example. An oxide semiconductor formed by a sputtering method using the above-mentioned target at a substrate temperature of higher than or equal to 100° C. and lower than or equal to 130° C. is referred to as sIGZO, and an oxide semiconductor formed by a sputtering method using the above-mentioned target with the substrate temperature set at room temperature (R.T.) is referred to as tIGZO. For example, sIGZO has one or both of the nano crystal (nc) crystal structure and the CAAC crystal structure. Furthermore, tIGZO has the nc crystal structure. Note that room temperature (R.T.) herein also refers to a temperature of the time when a substrate is not heated intentionally.

In this specification and the like, CAC-OS or CAC-metal oxide has a function of a conductor in a part of the material and has a function of a dielectric (or insulator) in another part of the material; as a whole, CAC-OS or CAC-metal oxide has a function of a semiconductor. In the case where CAC-OS or CAC-metal oxide is used in an active layer of a transistor, the conductor has a function of letting electrons (or holes) serving as carriers flow, and the dielectric has a function of not letting electrons serving as carriers flow. By the complementary action of the function as a conductor and the function as a dielectric, CAC-OS or CAC-metal oxide can have a switching function (on/off function). In the CAC-OS or CAC-metal oxide, separation of the functions can maximize each function.

In this specification and the like, CAC-OS or CAC-metal oxide includes conductor regions and dielectric regions. The conductor regions have the above-described function of the conductor, and the dielectric regions have the above-described function of the dielectric. In some cases, the conductor regions and the dielectric regions in the material are separated at the nanoparticle level. In some cases, the conductor regions and the dielectric regions are unevenly distributed in the material. When observed, the conductor regions are coupled in a cloud-like manner with their boundaries blurred, in some cases.

In other words, CAC-OS or CAC-metal oxide can be called a matrix composite or a metal matrix composite.

Furthermore, in the CAC-OS or CAC-metal oxide, the conductor regions and the dielectric regions each have a size of more than or equal to 0.5 nm and less than or equal to 10 nm, preferably more than or equal to 0.5 nm and less than or equal to 3 nm and are dispersed in the material, in some cases.

Unless otherwise specified, the off-state current in this specification and the like refers to a drain current of a transistor in the off state (also referred to as non-conduction state and cutoff state). Unless otherwise specified, the off state of an n-channel transistor means that a voltage (V_(gs)) between its gate and source is lower than the threshold voltage (V_(th)), and the off state of a p-channel transistor means that the gate-source voltage V_(gs) is higher than the threshold voltage V_(th). For example, the off-state current of an n-channel transistor sometimes refers to a drain current that flows when the gate-source voltage V_(gs) is lower than the threshold voltage V_(th).

The off-state current of a transistor depends on V_(gs) in some cases. Thus, “the off-state current of a transistor is lower than or equal to I” may mean “there is V_(gs) with which the off-state current of the transistor becomes lower than or equal to I”. Furthermore, “the off-state current of a transistor” means “the off-state current in an off state at predetermined V_(gs)”, “the off-state current in an off state at V_(gs) in a predetermined range”, “the off-state current in an off state at V_(gs) with which sufficiently reduced off-state current is obtained”, or the like.

As an example, the assumption is made of an n-channel transistor where the threshold voltage V_(th) is 0.5 V and the drain current is 1×10⁻⁹ A at V_(gs) of 0.5 V, 1×10⁻¹³ A at V_(gs) of 0.1 V, 1×10⁻¹⁹ A at V_(gs) of −0.5 V, and 1×10⁻²² A at V_(gs) of −0.8 V. The drain current of the transistor is 1×10⁻¹⁹ A or lower at V_(gs) of −0.5 V or at V_(gs) in the range of −0.8 V to −0.5 V; therefore, it can be said that the off-state current of the transistor is 1×10⁻¹⁹ A or lower. Since there is V_(gs) at which the drain current of the transistor is 1×10⁻²² A or lower, it may be said that the off-state current of the transistor is 1×10⁻²² A or lower.

In this specification and the like, the off-state current of a transistor with a channel width W is sometimes represented by a current value in relation to the channel width W or by a current value per given channel width (e.g., 1 μm). In the latter case, the off-state current may be expressed in the unit with the dimension of current per length (e.g., A/μm).

The off-state current of a transistor depends on temperature in some cases. Unless otherwise specified, the off-state current in this specification may be an off-state current at room temperature, 60° C., 85° C., 95° C., or 125° C. Alternatively, the off-state current may be an off-state current at a temperature at which the reliability required in a semiconductor device or the like including the transistor is ensured or a temperature at which the semiconductor device or the like including the transistor is used (e.g., temperature in the range of 5° C. to 35° C.). The description “an off-state current of a transistor is lower than or equal to I” may refer to a situation where there is V_(gs) at which the off-state current of a transistor is lower than or equal to I at room temperature, 60° C., 85° C., 95° C., 125° C., a temperature at which the reliability required in a semiconductor device or the like including the transistor is ensured, or a temperature at which the semiconductor device or the like including the transistor is used (e.g., temperature in the range of 5° C. to 35° C.).

The off-state current of a transistor depends on voltage V_(ds) between its drain and source in some cases. Unless otherwise specified, the off-state current in this specification may be an off-state current at V_(ds) of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V. Alternatively, the off-state current might be an off-state current at V_(ds) at which the required reliability of a semiconductor device or the like including the transistor is ensured or V_(ds) at which the semiconductor device or the like including the transistor is used. The description “an off-state current of a transistor is lower than or equal to I” may refer to a situation where there is V_(gs) at which the off-state current of a transistor is lower than or equal to I at V_(ds) of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V, V_(ds) at which the required reliability of a semiconductor device or the like including the transistor is ensured, or V_(ds) at which the semiconductor device or the like including the transistor is used.

In the above description of off-state current, a drain may be replaced with a source. That is, the off-state current sometimes refers to a current that flows through a source of a transistor in the off state.

In this specification and the like, the term “leakage current” sometimes expresses the same meaning as off-state current. In this specification and the like, the off-state current sometimes refers to a current that flows between a source and a drain when a transistor is off, for example.

In this specification and the like, a “semiconductor” can have characteristics of an “insulator” when the conductivity is sufficiently low, for example. Further, a “semiconductor” and an “insulator” cannot be strictly distinguished from each other in some cases because a border between the “semiconductor” and the “insulator” is not clear. Accordingly, a “semiconductor” in this specification and the like can be called an “insulator” in some cases. Similarly, an “insulator” in this specification and the like can be called a “semiconductor” in some cases. An “insulator” in this specification and the like can be called a “semi-insulator” in some cases.

In this specification and the like, a “semiconductor” can have characteristics of a “conductor” when the conductivity is sufficiently high, for example. Further, a “semiconductor” and a “conductor” cannot be strictly distinguished from each other in some cases because a border between the “semiconductor” and the “conductor” is not clear. Accordingly, a “semiconductor” in this specification and the like can be called a “conductor” in some cases. Similarly, a “conductor” in this specification and the like can be called a “semiconductor” in some cases.

In this specification and the like, an impurity in a semiconductor refers to an element that is not a main component of the semiconductor film. For example, an element with a concentration of lower than 0.1 atomic % is an impurity. If a semiconductor contains an impurity, the density of states (DOS) may be formed therein, the carrier mobility may be decreased, or the crystallinity may be decreased, for example. In the case where the semiconductor includes an oxide semiconductor, examples of the impurity which changes the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components; specific examples are hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. When the semiconductor is an oxide semiconductor, oxygen vacancies may be formed by entry of impurities such as hydrogen, for example. Furthermore, in the case where the semiconductor includes silicon, examples of the impurity which changes the characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.

Embodiment 1

In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof are described with reference to FIG. 1A to FIG. 12.

<1-1. Structure Example 1 of Semiconductor Device>

FIG. 1A is a top view of a transistor 100 that is a semiconductor device of one embodiment of the present invention. FIG. 1B is a cross-sectional view taken along a dashed-dotted line X1-X2 in FIG. 1A, and FIG. 1C is a cross-sectional view taken along a dashed-dotted line Y1-Y2 in FIG. 1A. Note that in FIG. 1A, some components of the transistor 100 (e.g., an insulating film serving as a gate insulating film) are not illustrated to avoid complexity. The direction of the dashed-dotted line X1-X2 may be called a channel length direction, and the direction of the dashed-dotted line Y1-Y2 may be called a channel width direction. As in FIG. 1A, some components are not illustrated in some cases in top views of transistors described below.

The transistor 100 includes a conductive film 104 over a substrate 102, an insulating film 106 over the substrate 102 and the conductive film 104, an insulating film 107 over the insulating film 106, an oxide semiconductor film 108 over the insulating film 107, a conductive film 112 a over the oxide semiconductor film 108, a conductive film 112 b over the oxide semiconductor film 108, an insulating film 114 over the oxide semiconductor film 108, the conductive film 112 a, and the conductive film 112 b, an insulating film 116 over the insulating film 114, a conductive film 120 a over the insulating film 116, and a conductive film 120 b over the insulating film 116.

The insulating film 106 and the insulating film 107 include an opening portion 151, and a conductive film 112 c that is electrically connected to the conductive film 104 through the opening portion 151 is formed over the insulating film 106 and the insulating film 107. The insulating films 114 and 116 include an opening portion 152 a that reaches the conductive film 112 b and an opening portion 152 b that reaches the conductive film 112 c.

The oxide semiconductor film 108 includes an oxide semiconductor film 108 b on the conductive film 104 side and an oxide semiconductor film 108 c over the oxide semiconductor film 108 b. The oxide semiconductor film 108 b and the oxide semiconductor film 108 c each include In, M (M is Al, Ga, Y, or Sn), and Zn.

The oxide semiconductor film 108 b preferably includes a region in which the atomic proportion of In is larger than the atomic proportion of M, for example. The oxide semiconductor film 108 c preferably includes a region in which the atomic proportion of In is smaller than the atomic proportion of In in the oxide semiconductor film 108 b.

When the oxide semiconductor film 108 b includes the region in which the atomic proportion of In is larger than the atomic proportion of M, the transistor 100 can have high field-effect mobility. Specifically, the field-effect mobility of the transistor 100 can exceed 10 cm²/Vs, preferably exceed 30 cm²/Vs.

For example, the use of the transistor with high field-effect mobility for a gate driver that generates a gate signal (specifically, a demultiplexer connected to an output terminal of a shift register included in a gate driver) allows a semiconductor device or a display device to have a narrow frame.

On the other hand, the oxide semiconductor film 108 b that includes the region in which the atomic proportion of In is larger than that of M makes it easier to change electrical characteristics of the transistor 100 in light irradiation. However, in the semiconductor device of one embodiment of the present invention, the oxide semiconductor film 108 c is formed over the oxide semiconductor film 108 b. The oxide semiconductor film 108 c including the region in which the atomic proportion of In is smaller than that in the oxide semiconductor film 108 b has larger Eg than the oxide semiconductor film 108 b. For this reason, the oxide semiconductor film 108 which is a layered structure of the oxide semiconductor film 108 b and the oxide semiconductor film 108 c has high resistance to a negative bias stress test with light irradiation.

Impurities such as hydrogen or moisture entering the channel region of the oxide semiconductor film 108, particularly the oxide semiconductor film 108 b adversely affect the transistor characteristics. Therefore, it is preferable that the amount of impurities such as hydrogen or moisture in the channel region of the oxide semiconductor film 108 b be as small as possible. Furthermore, oxygen vacancies formed in the channel region in the oxide semiconductor film 108 b adversely affect the transistor characteristics. For example, oxygen vacancies formed in the channel region in the oxide semiconductor film 108 b are bonded to hydrogen to serve as a carrier supply source. The carrier supply source generated in the channel region in the oxide semiconductor film 108 b causes a change in the electrical characteristics, typically, shift in the threshold voltage, of the transistor 100 including the oxide semiconductor film 108 b. Therefore, it is preferable that the amount of oxygen vacancies in the channel region in the oxide semiconductor film 108 b be as small as possible.

In view of this, one embodiment of the present invention is a structure in which insulating films over the oxide semiconductor film 108, specifically the insulating films 114 and 116 formed over the oxide semiconductor film 108, include excess oxygen. Oxygen or excess oxygen is transferred from the insulating films 114 and 116 to the oxide semiconductor film 108, whereby the oxygen vacancies in the oxide semiconductor film can be reduced.

In one embodiment of the present invention, stacked-layer structures are used as structures of the conductive films 120 a and 120 b so that excess oxygen is contained in the insulating films 114 and 116. Specifically, the conductive film 120 a includes an oxide conductive film 120 a_1 and a conductive film 120 a_2 over the oxide conductive film 120 a_1, and the conductive film 120 b includes an oxide conductive film 120 b_1 and a conductive film 120 b_2 over the oxide conductive film 120 b_1.

In the case where the stacked-layer structures are used, the following can be achieved. For example, by forming an oxide conductive film by a sputtering method in an atmosphere containing an oxygen gas in a step of forming the oxide conductive film 120 a_1 and the oxide conductive film 120 b_1, oxygen or excess oxygen can be added to the insulating film 116 over which the oxide conductive film is formed. Furthermore, owing to the conductive film 120 a_2 and the conductive film 120 b_2, light emitted from above can be less delivered to the oxide semiconductor film 108.

The conductive film 112 c and the conductive film 120 a are electrically connected to each other by an oxide conductive film 112 c_3 and the oxide conductive film 120 a_1. The conductive film 112 b and the conductive film 120 b are electrically connected to each other by an oxide conductive film 112 b_3 and the oxide conductive film 120 b_1.

Note that the conductive film 120 a_2 of the conductive film 120 a and the conductive film 120 b_2 of the conductive film 120 b are formed by processing the same conductive film. In other words, the conductive film 120 b_2 having the same composition as the conductive film 120 a_2 is formed in the opening portion 152 a.

An insulating film 118 is provided for the transistor 100. The insulating film 118 is formed so as to cover the insulating film 116, the conductive film 120 a_, and the conductive film 120 b.

Note that in the transistor 100, the insulating films 106 and 107 function as a first gate insulating film of the transistor 100, the insulating films 114 and 116 function as a second gate insulating film of the transistor 100, and the insulating film 118 functions as a protective insulating film of the transistor 100. In addition, in the transistor 100, the conductive film 104 functions as a first gate electrode, the conductive film 120 a functions as a second gate electrode, and the conductive film 120 b functions as a pixel electrode included in the display device. Furthermore, in the transistor 100, the conductive film 112 a functions as a source electrode, and the conductive film 112 b functions as a drain electrode. Furthermore, in the transistor 100, the conductive film 112 c functions as a connection electrode. In this specification and the like, the insulating films 106 and 107 are collectively referred to as a first insulating film, the insulating films 114 and 116 are collectively referred to as a second insulating film, and the insulating film 118 is referred to as a third insulating film in some cases.

The conductive film 112 a includes an oxide conductive film 112 a_1, a conductive film 112 a_2 over and in contact with the oxide conductive film 112 a_1, and an oxide conductive film 112 a_3 over and in contact with the conductive film 112 a_2. The conductive film 112 b includes an oxide conductive film 112 b_1, a conductive film 112 b_2 over and in contact with the oxide conductive film 112 b_1, and the oxide conductive film 112 b_3 over and in contact with the conductive film 112 b_2.

The conductive film 112 a_2 and the conductive film 112 b_2 each include copper. The oxide conductive film 112 a_1, the oxide conductive film 112 b_1, the oxide conductive film 112 a_3, and the oxide conductive film 112 b_3 each include a material that prevents diffusion of copper. An end portion of the oxide conductive film 112 a_1 includes a region located outward from an end portion of the conductive film 112 a_2. The oxide conductive film 112 a_3 covers a top surface and a side surface of the conductive film 112 a 2 and includes a region in contact with the oxide conductive film 112 a_1. An end portion of the oxide conductive film 112 b_1 includes a region located outward from an end portion of the conductive film 112 b_2. The oxide conductive film 112 b_3 covers a top surface and a side surface of the conductive film 112 b_2 and includes a region in contact with the oxide conductive film 112 b_1. An end portion of an oxide conductive film 112 c_1 includes a region located outward from an end portion of a conductive film 112 c_2. The oxide conductive film 112 c_3 covers a top surface and a side surface of the conductive film 112 c_2 and includes a region in contact with the oxide conductive film 112 c_1.

In the case where the conductive film 112 a and the conductive film 112 b have the above-described structures, impurities, typified by oxygen, can be prevented from diffusing into the conductive film 112 a_2 and the conductive film 112 b_2, and an increase in the wiring resistance due to heat or deterioration with time can be prevented. Furthermore, copper elements included in the conductive films 112 a and 112 b can be prevented from diffusing into the outside. Thus, a semiconductor device having stable electrical characteristics can be provided.

As illustrated in FIG. 1C, the conductive film 120 a serving as a second gate electrode is electrically connected to the conductive film 104 serving as a first gate electrode through the conductive film 112 c serving as a connection electrode. Accordingly, the conductive film 104 and the conductive film 120 a are supplied with the same potential.

As illustrated in FIG. 1C, the oxide semiconductor film 108 is positioned to face each of the conductive film 104 serving as a first gate electrode and the conductive film 120 a serving as a second gate electrode, and is sandwiched between the two films serving as gate electrodes. The length in the channel length direction and the length in the channel width direction of the conductive film 120 a are longer than the length in the channel length direction and the length in the channel width direction of the oxide semiconductor film 108, respectively. The whole oxide semiconductor film 108 is covered with the conductive film 120 a with the insulating films 114 and 116 positioned therebetween.

In other words, in the channel width direction of the transistor 100, the oxide semiconductor film 108 is surrounded by the conductive film 104 and the conductive film 120 a serving as a first gate electrode and a second gate electrode. The insulating films 106 and 107 serving as the first gate insulating film and the insulating films 114 and 116 serving as a second gate insulating film are provided between the oxide semiconductor film 108 and the conductive films 104 and 120 a.

Such a structure makes it possible that the oxide semiconductor film 108 included in the transistor 100 is electrically surrounded by electric fields of the conductive film 104 serving as a first gate electrode and the conductive film 120 a serving as a second gate electrode. A device structure of a transistor, like that of the transistor 100, in which electric fields of a first gate electrode and a second gate electrode electrically surround an oxide semiconductor film where a channel region is formed can be referred to as a surrounded channel (s-channel) structure.

Since the transistor 100 has the s-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film 108 by the conductive film 104 serving as a first gate electrode and the conductive film 120 a serving as a second gate electrode; therefore, the current drive capability of the transistor 100 can be improved and high on-state current characteristics can be obtained. Since the on-state current can be increased, the size of the transistor 100 can be reduced. In addition, since the oxide semiconductor film 108 is surrounded by the conductive film 104 serving as a first gate electrode and the conductive film 120 a serving as a second gate electrode in the transistor 100, the mechanical strength of the transistor 100 can be increased.

As described above, in the semiconductor device of one embodiment of the present invention, the stacked-layer structure of the oxide conductive film and the conductive film is used for the conductive film serving as a second gate electrode. Thus, oxygen can be added to the surface over which the conductive film serving as a second gate electrode is formed. Furthermore, the conductive film is connected to the connection electrode, whereby the contact resistance can be reduced. The use of such a structure can achieve a semiconductor device in which the variation in electrical characteristics is suppressed.

<1-2. Components of Semiconductor Device>

Components of the semiconductor device of this embodiment will be described below in detail.

[Substrate]

There is no particular limitation on the property of a material and the like of the substrate 102 as long as the material has heat resistance enough to withstand at least heat treatment to be performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, or a sapphire substrate may be used as the substrate 102. Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a compound semiconductor substrate made of silicon germanium or the like, an SOI substrate, or the like may be used as the substrate 102. Still alternatively, any of these substrates provided with a semiconductor element may be used as the substrate 102. In the case where a glass substrate is used as the substrate 102, a glass substrate having any of the following sizes can be used: the 6th generation (1500 mm×1850 mm), the 7th generation (1870 mm×2200 mm), the 8th generation (2200 mm×2400 mm), the 9th generation (2400 mm×2800 mm), and the 10th generation (2950 mm×3400 mm). Thus, a large-sized display device can be fabricated.

Alternatively, a flexible substrate may be used as the substrate 102, and the transistor 100 may be provided directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the transistor 100. The separation layer can be used when part or the whole of a semiconductor device formed over the separation layer is separated from the substrate 102 and transferred onto another substrate. In such a case, the transistor 100 can be transferred to a substrate having low heat resistance or a flexible substrate as well.

[Conductive Film]

The conductive film 104 serving as a first gate electrode, the conductive film 120 a_2 serving as a second gate electrode, and the conductive films 120 b_2 serving as a pixel electrode can each be formed using a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), and cobalt (Co); an alloy including any of these metal element as its component; an alloy including a combination of any of these elements; or the like.

The conductive film 104, the oxide conductive film 112 a_1, the oxide conductive film 112 b_1, the oxide conductive film 112 c 1, the oxide conductive film 120 a_1, the oxide conductive film 120 b_1, the oxide conductive film 112 a_3, the oxide conductive film 112 b_3, the oxide conductive film 112 c_3, the conductive film 120 a_2, and the conductive film 120 b_2 can be formed using an oxide conductor such as an oxide including indium and tin, an oxide including tungsten and indium, an oxide including tungsten, indium, and zinc, an oxide including titanium and indium, an oxide including titanium, indium, and tin, an oxide including indium and zinc, an oxide including silicon, indium, and tin, and an oxide including indium, gallium, and zinc.

Here, an oxide conductor is described. In this specification and the like, an oxide conductor may be referred to as OC. Oxygen vacancies are formed in an oxide semiconductor, and then hydrogen is added to the oxygen vacancies, so that a donor level is formed in the vicinity of the conduction band. This increases the conductivity of the oxide semiconductor; accordingly, the oxide semiconductor becomes a conductor. The oxide semiconductor having become a conductor can be referred to as an oxide conductor. An oxide semiconductor generally transmits visible light because of its large energy gap. An oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band. Therefore, the influence of absorption due to the donor level is small in an oxide conductor, and an oxide conductor has a visible light transmitting property comparable to that of an oxide semiconductor.

A Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used for the conductive films 104, 112 a_2, 112 b_2, 112 c_2, 120 a_2, and 120 b_2.

The Cu—X alloy film can be suitably used for the conductive film 112 a_2 of the conductive film 112 a, the conductive film 112 b_2 of the conductive film 112 b, and the conductive film 112 c_2 of the conductive film 112 c in particular. As the Cu—X alloy film, a Cu—Mn alloy film is particularly preferable. Note that one embodiment of the present invention is not limited thereto as long as the conductive film 112 b_2 and the conductive film 112 c_2 include at least copper.

The oxide conductive films 112 a_3, 112 b_3, and 112 c_3 may each have a structure where a film formed using the above-described metal element or alloy including the above-described metal element as its component and an oxide conductive film are stacked. For example, a stacked-layer structure of a tungsten film and an oxide including indium and tin over the tungsten film may be used.

[Insulating Films Serving as First Gate Insulating Film]

As each of the insulating films 106 and 107 serving as the first gate insulating film of the transistor 100, an insulating layer including at least one of the following films formed by a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, or the like can be used: a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. Note that instead of a stacked-layer structure of the insulating films 106 and 107, an insulating film of a single layer formed using a material selected from the above or an insulating film of three or more layers may be used.

The insulating film 106 functions as a blocking film which keeps out oxygen. For example, in the case where excess oxygen is supplied to the insulating film 107, the insulating film 114, the insulating film 116, and/or the oxide semiconductor film 108, the insulating film 106 can keep out oxygen.

Note that the insulating film 107 that is in contact with the oxide semiconductor film 108 that serves as a channel region of the transistor 100 is preferably an oxide insulating film and preferably includes a region including oxygen in excess of the stoichiometric composition (oxygen-excess region). In other words, the insulating film 107 is an insulating film capable of releasing oxygen. In order to provide the oxygen-excess region in the insulating film 107, the insulating film 107 is formed in an oxygen atmosphere, for example. As another example, the formed insulating film 107 is subjected to heat treatment in an oxygen atmosphere.

In the case where hafnium oxide is used for the insulating film 107, the following effect is attained. Hafnium oxide has higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, the insulating film 107 using hafnium oxide can have a larger thickness than the insulating film 107 using silicon oxide; thus, leakage current due to tunnel current can be low. That is, it is possible to provide a transistor with a low off-state current. Moreover, hafnium oxide with a crystal structure has a higher dielectric constant than hafnium oxide with an amorphous structure. Therefore, it is preferable to use hafnium oxide with a crystal structure in order to provide a transistor with low off-state current. Examples of the crystal structure include a monoclinic crystal structure and a cubic crystal structure. Note that one embodiment of the present invention is not limited to the above examples.

In this embodiment, a silicon nitride film is formed as the insulating film 106, and a silicon oxide film is formed as the insulating film 107. The silicon nitride film has a higher dielectric constant than a silicon oxide film and needs a larger thickness for capacitance equivalent to that of the silicon oxide film. Thus, when the silicon nitride film is included in the gate insulating film of the transistor 100, the thickness of the insulating film can be increased. This makes it possible to reduce a decrease in withstand voltage of the transistor 100 and furthermore to increase the withstand voltage, thereby reducing electrostatic discharge damage to the transistor 100.

[Oxide Semiconductor Film]

The oxide semiconductor film 108 can be formed using the materials described above.

In the case where the oxide semiconductor film 108 b includes In-M-Zn oxide, it is preferable that the atomic ratio of metal elements of a sputtering target used for forming the In-M-Zn oxide satisfy In>M. The atomic ratio of metal elements in such a sputtering target is, for example, In:M:Zn=2:1:3, In:M:Zn=3:1:2, or In:M:Zn=4:2:4.1.

In the case where the oxide semiconductor film 108 c is In-M-Zn oxide, it is preferable that the atomic ratio of metal elements of a sputtering target used for forming a film of the In-M-Zn oxide satisfy In≤M. The atomic ratio of metal elements in such a sputtering target is, for example, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:4, or In:M:Zn=1:3:6.

In the case where the oxide semiconductor film 108 b and the oxide semiconductor film 108 c are each In-M-Zn oxide, it is preferable to use a target including polycrystalline In-M-Zn oxide as the sputtering target. The use of the target including polycrystalline In-M-Zn oxide facilitates formation of the oxide semiconductor films 108 b and 108 c having crystallinity. Note that the atomic ratios of metal elements in the oxide semiconductor film 108 b and the oxide semiconductor film 108 c vary from the above atomic ratio of metal elements of the sputtering target within a range of ±40%. For example, when a sputtering target of the oxide semiconductor film 108 b with an atomic ratio of In to Ga and Zn of 4:2:4.1 is used, the atomic ratio of In to Ga and Zn in the oxide semiconductor film 108 b may be 4:2:3 or in the vicinity of 4:2:3.

The energy gap of the oxide semiconductor film 108 is 2 eV or more, preferably 2.5 eV or more, or further preferably 3 eV or more. With the use of an oxide semiconductor having such a wide energy gap, the off-state current of the transistor 100 can be reduced. In particular, an oxide semiconductor film having an energy gap more than or equal to 2 eV, preferably more than or equal to 2 eV and less than or equal to 3.0 eV is preferably used as the oxide semiconductor film 108 b, and an oxide semiconductor film having an energy gap more than or equal to 2.5 eV and less than or equal to 3.5 eV is preferably used as the oxide semiconductor film 108 c. Furthermore, the oxide semiconductor film 108 c preferably has a higher energy gap than the oxide semiconductor film 108 b.

Each thickness of the oxide semiconductor film 108 b and the oxide semiconductor film 108 c is more than or equal to 3 nm and less than or equal to 200 nm, preferably more than or equal to 3 nm and less than or equal to 100 nm, more preferably more than or equal to 3 nm and less than or equal to 50 nm.

An oxide semiconductor film with low carrier density is used as the oxide semiconductor film 108 c. For example, the carrier density of the oxide semiconductor film 108 c is lower than or equal to 1×10¹⁷/cm³, preferably lower than or equal to 1×10¹⁵/cm³, further preferably lower than or equal to 1×10¹³/cm³, still further preferably lower than or equal to 1×10¹¹/cm³.

Note that without limitation to the compositions and materials described above, a material with an appropriate composition can be used depending on required semiconductor characteristics and electrical characteristics (e.g., field-effect mobility and threshold voltage) of a transistor. Furthermore, in order to obtain required semiconductor characteristics of a transistor, it is preferable that the carrier density, the impurity concentration, the defect density, the atomic ratio of a metal element to oxygen, the interatomic distance, the density, and the like of the oxide semiconductor film 108 b and the oxide semiconductor film 108 c be set to be appropriate.

Note that it is preferable to use, as the oxide semiconductor film 108 b and the oxide semiconductor film 108 c, an oxide semiconductor film in which the impurity concentration is low and the density of defect states is low, in which case the transistor can have more excellent electrical characteristics. Here, the state in which impurity concentration is low and density of defect states is low (the amount of oxygen vacancies is small) is referred to as “highly purified intrinsic” or “substantially highly purified intrinsic”. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Thus, a transistor in which a channel region is formed in the oxide semiconductor film rarely has a negative threshold voltage (is rarely normally on). A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and accordingly has a low density of trap states in some cases. Further, the highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has an extremely low off-state current; even when an element has a channel width of 1×10⁶ μm and a channel length (L) of 10 μm, the off-state current can be less than or equal to the measurement limit of a semiconductor parameter analyzer, i.e., less than or equal to 1×10−13 A, at a voltage (drain voltage) between a source electrode and a drain electrode of from 1 V to 10 V.

Accordingly, the transistor in which the channel region is formed in the highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film can have a small variation in electrical characteristics and high reliability. Charge trapped by the trap states in the oxide semiconductor film takes a long time to be released and may behave like fixed charge. Thus, the transistor whose channel region is formed in the oxide semiconductor film having a high density of trap states has unstable electrical characteristics in some cases. As examples of the impurities, hydrogen, nitrogen, alkali metal, alkaline earth metal, and the like are given.

Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to a metal atom to form water, and also causes oxygen vacancies in a lattice from which oxygen is released (or a portion from which oxygen is released). Entry of hydrogen into the oxygen vacancy generates an electron serving as a carrier in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, a transistor including an oxide semiconductor film that contains hydrogen is likely to be normally on. Accordingly, it is preferable that hydrogen be reduced as much as possible in the oxide semiconductor film 108. Specifically, the hydrogen concentration of the oxide semiconductor film 108, which is measured by secondary ion mass spectrometry (SIMS), is lower than or equal to 2×10²⁰ atoms/cm³, preferably lower than or equal to 5×10¹⁹ atoms/cm³, further preferably lower than or equal to 1×10¹⁹ atoms/cm³, still further preferably lower than or equal to 5×10¹⁸ atoms/cm³, yet further preferably lower than or equal to 1×10¹⁸ atoms/cm³, even further preferably lower than or equal to 5×10¹⁷ atoms/cm³, or further preferably lower than or equal to 1×10¹⁶ atoms/cm³.

The oxide semiconductor film 108 b preferably includes a region in which hydrogen concentration is smaller than that in the oxide semiconductor film 108 c. A semiconductor device including the oxide semiconductor film 108 b having the region in which hydrogen concentration is smaller than that in the oxide semiconductor film 108 c can be increased in reliability.

When silicon or carbon that is one of elements belonging to Group 14 is included in the oxide semiconductor film 108 b, oxygen vacancy is increased in the oxide semiconductor film 108 b, and the oxide semiconductor film 108 b becomes an n-type film. Thus, the concentration of silicon or carbon (the concentration is measured by SIMS) in the oxide semiconductor film 108 b or the concentration of silicon or carbon (the concentration is measured by SIMS) in the vicinity of an interface with the oxide semiconductor film 108 b is set to be lower than or equal to 2×10¹⁸ atoms/cm³, preferably lower than or equal to 2×10¹⁷ atoms/cm³.

In addition, the concentration of alkali metal or alkaline earth metal of the oxide semiconductor film 108 b, which is measured by SIMS, is lower than or equal to 1×10¹⁸ atoms/cm³, preferably lower than or equal to 2×10¹⁶ atoms/cm³. Alkali metal and alkaline earth metal might generate carriers when bonded to an oxide semiconductor, in which case the off-state current of the transistor might be increased. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal of the oxide semiconductor film 108 b.

Furthermore, when including nitrogen, the oxide semiconductor film 108 b easily becomes n-type by generation of electrons serving as carriers and an increase of carrier density. Thus, a transistor including an oxide semiconductor film which contains nitrogen is likely to have normally-on characteristics. For this reason, nitrogen in the oxide semiconductor film is preferably reduced as much as possible; the concentration of nitrogen which is measured by SIMS is preferably set to be, for example, lower than or equal to 5×10¹⁸ atoms/cm³.

The oxide semiconductor film 108 b and the oxide semiconductor film 108 c may have a non-single-crystal structure, for example. Examples of the non-single-crystal structure include a c-axis-aligned crystalline oxide semiconductor (CAAC-OS) which is described later, a polycrystalline structure, a microcrystalline structure, and an amorphous structure. Among the non-single crystal structure, the amorphous structure has the highest density of defect states, whereas CAAC-OS has the lowest density of defect states.

[Insulating Films Serving as Second Gate Insulating Film]

The insulating films 114 and 116 serve as a second gate insulating film of the transistor 100. In addition, the insulating films 114 and 116 each have a function of supplying oxygen to the oxide semiconductor film 108. That is, the insulating films 114 and 116 contain oxygen. The insulating film 114 is an insulating film that is permeable to oxygen. Note that the insulating film 114 also serves as a film that relieves damage to the oxide semiconductor film 108 at the time of forming the insulating film 116 in a later step.

Silicon oxide, silicon oxynitride, or the like with a thickness greater than or equal to 5 nm and less than or equal to 150 nm, or preferably greater than or equal to 5 nm and less than or equal to 50 nm, can be used as the insulating film 114.

In addition, it is preferable that the amount of defects in the insulating film 114 be small and typically the spin density corresponding to a signal that appears at g=2.001 due to a dangling bond of silicon be lower than or equal to 3×10¹⁷ spins/cm³ by electron spin resonance (ESR) measurement. This is because if the density of defects in the insulating film 114 is high, oxygen is bonded to the defects and the amount of oxygen that permeates through the insulating film 114 is decreased.

Note that all oxygen entering the insulating film 114 from the outside does not move to the outside of the insulating film 114 and some oxygen remains in the insulating film 114. Furthermore, movement of oxygen occurs in the insulating film 114 in some cases in such a manner that oxygen enters the insulating film 114 and oxygen included in the insulating film 114 moves to the outside of the insulating film 114. When an oxide insulating film which is permeable to oxygen is formed as the insulating film 114, oxygen released from the insulating film 116 provided over the insulating film 114 can be moved to the oxide semiconductor film 108 through the insulating film 114.

Oxygen released from the insulating film 116 is diffused toward the oxide semiconductor film 108 and also toward the conductive film 112 a, the conductive film 112 b, and the conductive film 112 c. In one embodiment of the present invention, the oxide conductive film 112 a_3, the oxide conductive film 112 b_3, and the oxide conductive film 112 c_3 each include an oxide conductive film. The oxide conductive film 112 a_3, the oxide conductive film 112 b_3, and the oxide conductive film 112 c_3 can keep out excess oxygen that is diffused from the silicon oxynitride film. Thus, excess oxygen can be diffused from the silicon oxynitride film into the oxide semiconductor film 108 effectively.

FIGS. 42A to 42E each show the released amount of a mass-to-charge ratio M/z=32 corresponding to an oxygen molecule of a sample measured by thermal desorption spectroscopy (TDS). The horizontal axis indicates the temperature of a sample, and the vertical axis indicates the intensity representing the released amount. In each of FIGS. 42A to 42E, emission characteristics 201 of a sample where a 100-nm-thick silicon oxynitride film was formed over a glass substrate are shown. Furthermore, emission characteristics 202 of a sample where a barrier layer was formed over a 100-nm-thick silicon oxynitride film over a glass substrate and the barrier layer was then removed after heat treatment was performed at 200° C. in a nitrogen atmosphere are shown. Furthermore, emission characteristics 203 of a sample where a barrier layer was formed over a 100-nm-thick silicon oxynitride film over a glass substrate and the barrier layer was then removed after heat treatment was performed at 250° C. in a nitrogen atmosphere are shown.

In FIG. 42A, a copper film was used as the barrier layer. In FIG. 42B, a titanium nitride film was used as the barrier layer. In FIG. 42C, a tantalum nitride film was used as the barrier layer. In FIG. 42D, a low-resistance ITSO film formed using a target of an oxide including indium, tin, and silicon (also referred to as ITSO) (In₂O₃:SnO₂:SiO₂=85:10:5 [weight %]) was used as the barrier layer. In FIG. 42E, a low-resistance IGZO film formed using an In—Ga—Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) was used as the barrier layer. The thickness of the barrier layer is 50 nm in each of FIGS. 42A to 42D and 100 nm in FIG. 42E. The barrier layer is metal in each of FIGS. 42A to 42C and an oxide conductive film in each of FIGS. 42D and 42E.

FIGS. 42A to 42E suggest that the sample of the barrier layer formed of an oxide conductor releases more oxygen after the heat treatment than the sample of the barrier layer formed of a metal.

The results shown in FIGS. 42A to 42E reveal that, owing to the oxide conductive film 112 a_3, the oxide conductive film 112 b_3, and the oxide conductive film 1120 in FIGS. 1A to 1C, excess oxygen can be supplied effectively from the silicon oxynitride film to the channel region of the oxide semiconductor film, so that oxygen vacancy in the oxide semiconductor film can be reduced. Furthermore, oxygen can be prevented from diffusing from the oxide semiconductor film 108 into the oxide conductive film 112 a and the oxide conductive film 112 b. That is, carriers can be prevented from being formed in a region near the source and the drain in the channel of the oxide semiconductor film, which can prevent effective channel lengths from being shortened or varied.

Note that the insulating film 114 can be formed using an oxide insulating film having a low density of states due to nitrogen oxide. Note that the density of states due to nitrogen oxide can be formed between the energy of the valence band maximum (E_(v) _(_) _(os)) and the energy of the conduction band minimum (E_(c) _(_) _(os)) of the oxide semiconductor film. A silicon oxynitride film that releases less nitrogen oxide, an aluminum oxynitride film that releases less nitrogen oxide, and the like can be used as the above oxide insulating film.

Note that a silicon oxynitride film that releases less nitrogen oxide is a film of which the amount of released ammonia is larger than the amount of released nitrogen oxide in TDS; the amount of released ammonia is typically greater than or equal to 1×10¹⁸/cm³ and less than or equal to 5×10¹⁹/cm³. Note that the amount of released ammonia is the amount of ammonia released by heat treatment with which the surface temperature of the film becomes higher than or equal to 50° C. and lower than or equal to 650° C., preferably higher than or equal to 50° C. and lower than or equal to 550° C.

Nitrogen oxide (NO_(x); x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO₂ or NO, forms levels in the insulating film 114, for example. The level is positioned in the energy gap of the oxide semiconductor film 108. Therefore, when nitrogen oxide is diffused to the interface between the insulating film 114 and the oxide semiconductor film 108, an electron is in some cases trapped by the level on the insulating film 114 side. As a result, the trapped electron remains at or near the interface between the insulating film 114 and the oxide semiconductor film 108; thus, the threshold voltage of the transistor is shifted in the positive direction.

Nitrogen oxide reacts with ammonia and oxygen in heat treatment. Since nitrogen oxide included in the insulating film 114 reacts with ammonia included in the insulating film 116 in heat treatment, nitrogen oxide included in the insulating film 114 is reduced. Therefore, an electron is hardly trapped at the interface between the insulating film 114 and the oxide semiconductor film 108.

By using such an oxide insulating film, the insulating film 114 can reduce the shift in the threshold voltage of the transistor, which leads to a smaller change in the electrical characteristics of the transistor.

Note that in an ESR spectrum at 100 K or lower of the insulating film 114, by heat treatment of a manufacturing process of the transistor, typically heat treatment at a temperature higher than or equal to 300° C. and lower than 350° C., a first signal that appears at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039, a second signal that appears at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003, and a third signal that appears at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966 are observed. The split width of the first and second signals and the split width of the second and third signals that are obtained by ESR measurement using an X-band are each approximately 5 mT. The sum of the spin densities of the first signal that appears at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039, the second signal that appears at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003, and the third signal that appears at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966 is lower than 1×10¹⁸ spins/cm³, typically higher than or equal to 1×10¹⁷ spins/cm³ and lower than 1×10¹⁸ spins/cm³.

In the ESR spectrum at 100 K or lower, the sum of the spin densities of the first signal that appears at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039, the second signal that appears at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003, and the third signal that appears at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966 corresponds to the sum of the spin densities of signals attributed to nitrogen oxide (NO_(x); x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2). Typical examples of the nitrogen oxide include nitrogen monoxide and nitrogen dioxide. Accordingly, the lower the sum of the spin densities of the first signal that appears at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039, the second signal that appears at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003, and the third signal that appears at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966 is, the lower the content of nitrogen oxide in the oxide insulating film is.

The nitrogen concentration of the above-described oxide insulating film measured by SIMS is lower than or equal to 6×10²⁰ atoms/cm³.

The above oxide insulating film is formed by a PECVD method at a substrate temperature higher than or equal to 220° C. and lower than or equal to 350° C. with the use of silane and dinitrogen monoxide, whereby a dense and hard film can be formed.

The insulating film 116 is formed using an oxide insulating film that includes oxygen in excess of that in the stoichiometric composition. Part of oxygen is released by heating from the oxide insulating film containing oxygen in excess of that in the stoichiometric composition. The oxide insulating film including oxygen in excess of that in the stoichiometric composition is an oxide insulating film of which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0×10¹⁹ atoms/cm³, or preferably greater than or equal to 3.0×10²⁰ atoms/cm³, in TDS analysis. Note that the film surface temperature in TDS is preferably higher than or equal to 100° C. and lower than or equal to 700° C., or higher than or equal to 100° C. and lower than or equal to 500° C.

A silicon oxide film, a silicon oxynitride film, or the like with a thickness greater than or equal to 30 nm and less than or equal to 500 nm, or preferably greater than or equal to 50 nm and less than or equal to 400 nm, can be used as the insulating film 116.

It is preferable that the amount of defects in the insulating film 116 be small, and typically the spin density corresponding to a signal which appears at g=2.001 due to a dangling bond of silicon be lower than 1.5×10¹⁸ spins/cm³, or further preferably lower than or equal to 1×10¹⁸ spins/cm³ by ESR measurement. Note that the insulating film 116 is provided more apart from the oxide semiconductor film 108 than the insulating film 114 is; thus, the insulating film 116 may have higher density of defects than the insulating film 114.

Further, the insulating films 114 and 116 can be formed using insulating films formed of the same kinds of materials; thus, a boundary between the insulating films 114 and 116 cannot be clearly observed in some cases. Thus, in this embodiment, the boundary between the insulating films 114 and 116 is shown by a dashed line. Although a two-layer structure of the insulating films 114 and 116 is described in this embodiment, the present invention is not limited to this. For example, a single-layer structure of only the insulating film 114 or a layered structure of three or more layers may be employed.

[Insulating Film Serving as Protective Insulating Film]

The insulating film 118 serves as a protective insulating film of the transistor 100.

The insulating film 118 includes one or both of hydrogen and nitrogen. The insulating film 118 includes nitrogen and silicon. The insulating film 118 has a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. It is possible to prevent outward diffusion of oxygen from the oxide semiconductor film 108, outward diffusion of oxygen included in the insulating films 114 and 116, and entry of hydrogen, water, or the like into the oxide semiconductor film 108 from the outside by providing the insulating film 118.

A nitride insulating film can be used as the insulating film 118, for example. The nitride insulating film is formed using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like.

Although the variety of films such as the conductive films, the insulating films, the oxide semiconductor film, and the metal oxide film which are described above can be formed by a sputtering method or a PECVD method, such films may be formed by another method, e.g., a thermal CVD method. A metal organic chemical vapor deposition (MOCVD) method or an atomic layer deposition (ALD) method may be employed as an example of a thermal CVD method.

A thermal CVD method has an advantage that no defect due to plasma damage is generated since it does not utilize plasma for forming a film.

Deposition by a thermal CVD method may be performed in such a manner that a source gas and an oxidizer are supplied to a chamber at a time, the pressure in the chamber is set to an atmospheric pressure or a reduced pressure, and they are reacted with each other in the vicinity of the substrate or over the substrate.

Deposition by an ALD method may be performed in such a manner that the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, source gases for reaction are sequentially introduced into the chamber, and then the sequence of the gas introduction is repeated.

The variety of films such as the conductive films, the insulating films, the oxide semiconductor film, and the metal oxide film in this embodiment can be formed by a thermal CVD method such as an MOCVD method or an ALD method. In the case where an In—Ga—ZnO film is formed, for example, trimethylindium, trimethylgallium, and dimethylzinc are used. Note that the chemical formula of trimethylindium is In(CH₃)₃. The chemical formula of trimethylgallium is Ga(CH₃)₃. The chemical formula of dimethylzinc is Zn(CH₃)₂. Without limitation to the above combination, triethylgallium (chemical formula: Ga(C₂H₅)₃) can be used instead of trimethylgallium and diethylzinc (chemical formula: Zn(C₂H₅)₂) can be used instead of dimethylzinc.

For example, in the case where a hafnium oxide film is formed by a deposition apparatus using an ALD method, two kinds of gases, i.e., ozone (O₃) as an oxidizer and a source gas which is obtained by vaporizing liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakis(dimethylamide)hafnium (TDMAH)) are used. Note that the chemical formula of tetrakis(dimethylamide)hafnium is Hf[N(CH₃)₂]₄. Examples of another material liquid include tetrakis(ethylmethylamide)hafnium.

For example, in the case where an aluminum oxide film is formed by a deposition apparatus using an ALD method, two kinds of gases, e.g., H₂O as an oxidizer and a source gas which is obtained by vaporizing liquid containing a solvent and an aluminum precursor compound (e.g., trimethylaluminum (TMA)) are used. Note that the chemical formula of trimethylaluminum is Al(CH₃)₃. Examples of another material liquid include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

For example, in the case where a silicon oxide film is formed by a deposition apparatus using ALD, hexachlorodisilane is adsorbed on a surface where a film is to be formed, chlorine contained in the adsorbate is removed, and radicals of an oxidizing gas (e.g., O₂ or dinitrogen monoxide) are supplied to react with the adsorbate.

For example, in the case where a tungsten film is formed using a deposition apparatus employing ALD, a WF₆ gas and a B₂H₆ gas are sequentially introduced plural times to form an initial tungsten film, and then a WF₆ gas and an H₂ gas are introduced at a time, so that a tungsten film is formed. Note that an SiH₄ gas may be used instead of a B₂H₆ gas.

For example, in the case where an oxide semiconductor film, e.g., an In—Ga—ZnO film is formed with a deposition apparatus using an ALD method, an In(CH₃)₃ gas and an O₃ gas are sequentially introduced a plurality of times to form an In—O layer, then a Ga(CH₃)₃ gas and an O₃ gas are used to form a GaO layer, and then a Zn(CH₃)₂ gas and an O₃ gas are used to form a ZnO layer. Note that the order of these layers is not limited to this example. A mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed by mixing of these gases. An H₂O gas which is obtained by bubbling with an inert gas such as Ar may be used instead of an O₃ gas, but it is preferable to use an O₃ gas, which does not contain H. Instead of an In(CH₃)₃ gas, an In(C₂H₅)₃ gas may be used. Instead of a Ga(CH₃)₃ gas, a Ga(C₂H₅)₃ gas may be used. Further, a Zn(CH₃)₂ gas may be used.

<1-3. Structure Example 2 of Semiconductor Device>

Next, modification examples of the transistor 100 shown in FIGS. 1A to 1C are described with reference to FIGS. 2A and 2B, FIGS. 3A and 3B, FIGS. 4A and 4B, FIGS. 5A and 5B, and FIGS. 6A and 6B.

FIGS. 2A and 2B are cross-sectional views of a transistor 100A that is a modification example of the transistor 100 shown in FIGS. 1B and 1C. FIGS. 3A and 3B are cross-sectional views of a transistor 100B that is a modification example of the transistor 100 shown in FIGS. 1B and 1C. FIGS. 4A and 4B are cross-sectional views of a transistor 100C that is a modification example of the transistor 100 shown in FIGS. 1B and 1C. FIGS. 5A and 5B are cross-sectional views of a transistor 100D that is a modification example of the transistor 100 shown in FIGS. 1B and 1C. FIGS. 6A and 6B are cross-sectional views of a transistor 100E that is a modification example of the transistor 100 shown in FIGS. 1B and 1C.

The transistor 100A shown in FIGS. 2A and 2B is different from the transistor 100 shown in FIGS. 1B and 1C in that the oxide semiconductor film 108 of the transistor 100A has a three-layer structure. Specifically, the oxide semiconductor film 108 of the transistor 100A includes an oxide semiconductor film 108 a, an oxide semiconductor film 108 b over the oxide semiconductor film 108 a, and an oxide semiconductor film 108 c over the oxide semiconductor film 108 b.

The transistor 100B shown in FIGS. 3A and 3B is different from the transistor 100 shown in FIGS. 1B and 1C in that the oxide semiconductor film 108 of the transistor 100B has a single-layer structure. Specifically, the transistor 100B includes the oxide semiconductor film 108 b.

The transistor 100C shown in FIGS. 4A and 4B is different from the transistor 100 shown in FIGS. 1B and 1C in the shape of the oxide semiconductor film 108. Specifically, in the oxide semiconductor film 108 c of the transistor 100, the thickness of a region that is not covered by the conductive films 112 a and 112 b is small in the figure. In other words, part of the oxide semiconductor film has a recessed portion. In contrast, in the oxide semiconductor film 108 c of the transistor 100C, the thickness of a region that is not covered by the conductive films 112 a and 112 b is not reduced in the figure. In other words, part of the oxide semiconductor film does not have a recessed portion.

The transistor 100D shown in FIGS. 5A and 5B is different from the transistor 100 shown in FIGS. 1B and 1C in the structures of the conductive films 112 a, 112 b, and 112 c. Specifically, the conductive films 112 a, 112 b, and 112 c of the transistor 100D are formed of oxide conductive films. In that case, although the wiring resistance of the conductive films 112 a, 112 b, and 112 c is increased, the channel region of the oxide semiconductor film is exposed to more oxygen plasma in forming the conductive films 112 a, 112 b, and 112 c, whereby excess oxygen can be supplied effectively.

The transistor 100E shown in FIGS. 6A and 6B is a channel-protective transistor. An insulating film 115 serving as a channel protective film is provided over the oxide semiconductor film 108. The insulating film 115 can be formed using a material similar to that of the insulating film 114. Note that in the case where the insulating film 115 is provided, a structure may be used in which the insulating film 114 is not provided and the insulating film 116 is provided over the conductive films 112 a and 112 b and the insulating film 115.

In the semiconductor device of the present invention, the stacked-layer structure of the oxide semiconductor films, the shape of the oxide semiconductor film, the stacked-layer structure of the conductive films, and the like can be changed as described above. The structures of the transistors of this embodiment can be freely combined with each other.

<1-4. Manufacturing Method of Semiconductor Device>

Next, a method for manufacturing the transistor 100 that is a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 7A to 7C, FIGS. 8A to 8C, FIGS. 9A to 9C, FIG. 10, FIGS. 11A to 11C, and FIG. 12.

Note that FIGS. 7A to 7C, FIGS. 8A to 8C, FIGS. 9A to 9C, FIG. 10, FIGS. 11A to 11C, and FIG. 12 are cross-sectional views illustrating a method for manufacturing the semiconductor device. In FIGS. 7A to 7C, FIGS. 8A to 8C, FIGS. 9A to 9C, FIG. 10, FIGS. 11A to 11C, and FIG. 12, the left parts show the cross-sectional views in the channel length direction, and the right parts show the cross-sectional views in the channel width direction.

First, a conductive film is formed over the substrate 102 and processed through a lithography process and an etching process, whereby the conductive film 104 that functions as the first gate electrode is formed. Then, the insulating films 106 and 107 serving as the first gate insulating film are formed over the conductive film 104 (see FIG. 7A).

In this embodiment, a glass substrate is used as the substrate 102, and as the conductive film 104 serving as the first gate electrode, a 50-nm-thick titanium film and a 200-nm-thick copper film are each formed by a sputtering method. As the insulating film 106, a 400-nm-thick silicon nitride film is formed by a PECVD method. As the insulating film 107, a 50-nm-thick silicon oxynitride film is formed by a PECVD method.

Note that the insulating film 106 can have a stacked-layer structure of silicon nitride films. Specifically, the insulating film 106 can have a three-layer structure of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. An example of the three-layer structure is as follows.

For example, the first silicon nitride film can be formed to have a thickness of 50 nm under the conditions where silane at a flow rate of 200 sccm, nitrogen at a flow rate of 2000 sccm, and an ammonia gas at a flow rate of 100 sccm are supplied as a source gas to a reaction chamber of a PECVD apparatus, the pressure in the reaction chamber is controlled to 100 Pa, and the power of 2000 W is supplied using a 27.12 MHz high-frequency power source.

The second silicon nitride film can be formed to have a thickness of 300 nm under the conditions where silane at a flow rate of 200 sccm, nitrogen at a flow rate of 2000 sccm, and an ammonia gas at a flow rate of 2000 sccm are supplied as a source gas to the reaction chamber of the PECVD apparatus, the pressure in the reaction chamber is controlled to 100 Pa, and the power of 2000 W is supplied using a 27.12 MHz high-frequency power source.

The third silicon nitride film can be formed to have a thickness of 50 nm under the conditions where silane at a flow rate of 200 sccm and nitrogen at a flow rate of 5000 sccm are supplied as a source gas to the reaction chamber of the PECVD apparatus, the pressure in the reaction chamber is controlled to 100 Pa, and the power of 2000 W is supplied using a 27.12 MHz high-frequency power source.

Note that the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can each be formed at a substrate temperature of 350° C. or lower.

In the case where a conductive film including copper is used as the conductive film 104, the use of the three-layer structure of silicon nitride films for the insulating film 106 provides the following effect.

The first silicon nitride film can inhibit diffusion of copper from the conductive film 104. The second silicon nitride film has a function of releasing hydrogen and can improve withstand voltage of the insulating film that serves as a gate insulating film. The third silicon nitride film releases a small amount of hydrogen and can inhibit diffusion of hydrogen released from the second silicon nitride film.

The insulating film 107 is preferably an insulating film including oxygen to improve characteristics of an interface with the oxide semiconductor film 108 (specifically the oxide semiconductor film 108 b) formed later. Oxygen may be added to the insulating film 107 after the insulating film 107 is formed. As the oxygen, an oxygen radical, an oxygen atom, an oxygen atomic ion, an oxygen molecular ion, or the like may be added to the insulating film 107. The oxygen can be added by an ion doping method, an ion implantation method, a plasma treatment method, or the like.

Next, an oxide semiconductor film 108 b_0 and an oxide semiconductor film 108 c_0 are formed over the insulating film 107 (see FIGS. 7B and 7C).

Note that FIG. 7B is a schematic cross-sectional view showing an inner portion of a deposition apparatus when the oxide semiconductor film 108 b_0 is formed over the insulating film 107. In FIG. 7B, a sputtering apparatus is used as the deposition apparatus, and a target 191 placed inside the sputtering apparatus and plasma 192 formed under the target 191 are schematically illustrated.

When the oxide semiconductor film 108 b_0 is formed, plasma discharge is performed in an atmosphere containing an oxygen gas. At this time, oxygen is added to the insulating film 107 over which the oxide semiconductor film 108 b_0 is to be formed. When the oxide semiconductor film 108 b_0 is formed, an inert gas (e.g., a helium gas, an argon gas, or a xenon gas) and the oxygen gas may be mixed.

The oxygen gas is mixed at least when the oxide semiconductor film 108 b_0 is formed. The proportion of the oxygen gas in a deposition gas for forming the oxide semiconductor film 108 b_0 is higher than 0% and lower than or equal to 100%, preferably higher than or equal to 10% and lower than or equal to 100%, more preferably higher than or equal to 30% and lower than or equal to 100%.

In FIG. 7B, oxygen or excess oxygen to be added to the insulating film 107 is schematically shown by arrows of broken lines.

The oxide semiconductor films 108 b_0 and 108 c_0 may be formed at the same substrate temperature or different substrate temperatures. Note that the oxide semiconductor films 108 b_0 and 108 c_0 are preferably formed at the same substrate temperature, in which case the manufacturing cost can reduced.

The oxide semiconductor film 108 is formed at a substrate temperature higher than or equal to room temperature and lower than 340° C., preferably higher than or equal to room temperature and lower than or equal to 300° C., further preferably higher than or equal to 100° C. and lower than or equal to 250° C., still further preferably higher than or equal to 100° C. and lower than or equal to 200° C., for example. The oxide semiconductor film 108 is formed while being heated, so that the crystallinity of the oxide semiconductor film 108 can be increased. On the other hand, in the case where a large-sized glass substrate (e.g., the 6th generation to the 10th generation) is used as the substrate 102 and the oxide semiconductor film 108 is formed at a substrate temperature higher than or equal to 150° C. and lower than 340° C., the substrate 102 might be changed in shape (distorted or warped). In the case where a large-sized glass substrate is used, the change in the shape of the glass substrate can be suppressed by forming the oxide semiconductor film 108 at a substrate temperature higher than or equal to 100° C. and lower than 150° C.

In addition, increasing the purity of a sputtering gas is necessary. For example, as an oxygen gas or an argon gas used for a sputtering gas, a gas which is highly purified to have a dew point of −40° C. or lower, preferably −80° C. or lower, further preferably −100° C. or lower, still further preferably −120° C. or lower is used, whereby entry of moisture or the like into the oxide semiconductor film can be minimized.

When the oxide semiconductor film is formed by a sputtering method, each chamber of a sputtering apparatus is preferably evacuated to a high vacuum (to the degree of approximately 5×10⁻⁷ Pa to 1×10⁻⁴ Pa, for example) by an adsorption vacuum pump such as a cryopump so that water and the like acting as impurities for the oxide semiconductor film are removed as much as possible. Alternatively, a turbo molecular pump and a cold trap are preferably combined so as to prevent a backflow of a gas, especially a gas containing carbon or hydrogen from an exhaust system to the inside of the chamber.

After the oxide semiconductor film 108 b_0 is formed, the oxide semiconductor film 108 c_0 is successively formed over the oxide semiconductor film 108 b_0. The oxide semiconductor film 108 c_0 can be formed under conditions similar to those used for forming the oxide semiconductor film 108 b_0. Note that the conditions for forming the oxide semiconductor film 108 b_0 may be the same or different from the conditions for forming the oxide semiconductor film 108 c_0.

In this embodiment, the oxide semiconductor film 108 b_0 is formed by a sputtering method using an In—Ga—Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) and then the oxide semiconductor film 108 c_0 is successively formed in a vacuum by a sputtering method using an In—Ga—Zn metal oxide target (In:Ga:Zn=1:1:1.2 [atomic ratio]). The substrate temperature when the oxide semiconductor film 108 b_0 is formed is set to 170° C., and the substrate temperature when the oxide semiconductor film 108 c_0 is formed is set to 170° C. As the deposition gas for forming the oxide semiconductor film 108 b_0, an oxygen gas at a flow rate of 60 sccm and an argon gas at a flow rate of 140 sccm are used. As the deposition gas for forming the oxide semiconductor film 108 c_0, an oxygen gas at a flow rate of 100 sccm and an argon gas at a flow rate of 100 sccm are used.

Next, the oxide semiconductor film 108 b_0 and the oxide semiconductor film 108 c_0 are processed into desired shapes, so that the island-shaped oxide semiconductor films 108 b and 108 c are formed. Note that in this embodiment, the oxide semiconductor film 108 includes the oxide semiconductor films 108 b and 108 c (see FIG. 8A).

Heat treatment (hereinafter referred to as first heat treatment) is preferably performed after the oxide semiconductor film 108 is formed. By the first heat treatment, hydrogen, water, and the like contained in the oxide semiconductor film 108 can be reduced. Note that the heat treatment for the purpose of reducing hydrogen, water, and the like may be performed before the oxide semiconductor film 108 is processed into an island shape. Note that the first heat treatment is one kind of treatment for increasing the purity of the oxide semiconductor film.

The first heat treatment can be performed at a temperature of, for example, higher than or equal to 150° C. and lower than the strain point of the substrate, preferably higher than or equal to 200° C. and lower than or equal to 450° C., further preferably higher than or equal to 250° C. and lower than or equal to 350° C.

Moreover, an electric furnace, an RTA apparatus, or the like can be used for the first heat treatment. With the use of an RTA apparatus, the heat treatment can be performed at a temperature higher than or equal to the strain point of the substrate if the heating time is short. Therefore, the heat treatment time can be shortened. The first heat treatment may be performed under an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, further preferably 10 ppb or less), or a rare gas (e.g., argon, helium). The atmosphere of nitrogen, oxygen, ultra-dry air, or a rare gas preferably does not contain hydrogen, water, and the like. Furthermore, after heat treatment performed under a nitrogen atmosphere or a rare gas atmosphere, heat treatment may be additionally performed in an oxygen atmosphere or an ultra-dry air atmosphere. As a result, hydrogen, water, and the like can be released from the oxide semiconductor film and oxygen can be supplied to the oxide semiconductor film at the same time. Consequently, oxygen vacancies in the oxide semiconductor film can be reduced.

Then, the opening portion 151 is formed in a desired region of the insulating film 106 and the insulating film 107. Note that the opening portion 151 reaches the conductive film 104 (see FIG. 8B).

The opening portion 151 can be formed by one or both of a dry etching method and a wet etching method. In this embodiment, the opening portion 151 is formed by a dry etching method.

Then, conductive films 112_1 and 112_2 are formed over the insulating film 107, the oxide semiconductor film 108, and the conductive film 104 (see FIG. 8C).

In this embodiment, an indium zinc oxide film is formed with a thickness of 30 nm by a sputtering method as the conductive film 112_1. Furthermore, a copper film is formed with a thickness of 200 nm by a sputtering method as the conductive film 1122.

Then, masks 141 a, 141 b, and 141 c are formed in desired regions over the conductive film 112_2. Then, the conductive film 112_2 is processed using the masks 141 a, 141 b, and 141 c to form the island-shaped conductive films 112 a_2, 112 b_2, and 112 c_2 (see FIG. 9A).

In this embodiment, the conductive film 112_2 is processed with a wet etching apparatus. Note that the method for processing the conductive film 112_2 is not limited thereto, and a dry etching apparatus may be used, for example.

Then, the masks 141 a, 141 b, and 141 c are removed. Then, a conductive film 1123 is formed over the conductive film 112_1 and the conductive films 112 a_2, 112 b_2, and 112 c_2 (see FIG. 9B).

In this embodiment, a 10-nm-thick indium zinc oxide film is formed by a sputtering method as the conductive film 112_3. By the formation of the conductive film 112_3, a structure is obtained in which the conductive films 112 a_2, 112 b_2, and 112 c_2 are surrounded by the conductive film 112_1 and the conductive film 112_3. Owing to the structure in which the conductive films 112 a_2, 112 b_2, and 112 c_2 are surrounded by the conductive film 112_1 and the conductive film 112_3, a copper element included in the conductive films 112 a_2, 112 b_2, and 112 c_2 can be prevented from diffusing into the outside, in particular, the oxide semiconductor film 108. Note that the conductive film 112_3 may have a stacked-layer structure of a metal film and an oxide conductive film.

Then, masks 142 a, 142 b, and 142 c are formed in desired regions over the conductive film 112_3. Then, the conductive film 112_1 and the conductive film 112_3 are processed using the masks 142 a, 142 b, and 142 c to form the island-shaped oxide conductive film 112 a_1, the island-shaped oxide conductive film 112 b_1, the island-shaped oxide conductive film 112 c_1, the island-shaped oxide conductive film 112 a_3, the island-shaped oxide conductive film 112 b_3, and the island-shaped oxide conductive film 112 c_3. By the step, the conductive film 112 a including the oxide conductive film 112 a_1, the conductive film 112 a_2, and the oxide conductive film 112 a_3, the conductive film 112 b including the oxide conductive film 112 b_1, the conductive film 112 b 2, and the oxide conductive film 112 b_3, and the conductive film 112 c including the oxide conductive film 112 c_1, the conductive film 112 c_2, and the oxide conductive film 112 c_3 are formed (see FIG. 9C).

In one embodiment of the present invention, the conductive film 112_1 and the conductive film 112_3 are processed with a wet etching apparatus. Thus, the oxide semiconductor film thereunder is exposed. FIGS. 41A and 41B show etching rates of an oxide semiconductor film and oxide conductive films. FIG. 41A shows wet etching rates thereof with respect to a mixed acid of phosphoric acid, nitric acid, and acetic acid, i.e., a PAN etchant, at a chemical solution temperature of 30° C. FIG. 41B shows wet etching rates thereof with respect to a copper etchant, a mixed solution of an additive including chelate or the like, hydrogen peroxide, and inorganic acid.

An oxide semiconductor film 301 was formed by a sputtering method using an In—Ga—Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) and a film formation gas with a flow rate ratio of argon:oxygen=7:3 at a substrate temperature of 170° C. in the film formation. An oxide conductive film 302 was formed by a sputtering method using an In—Zn metal oxide target (In:Zn=2:1 [atomic ratio]) at a substrate temperature of 25° C. in the film formation. The oxide conductive film 302 was formed using a film formation gas with a flow rate ratio of argon:oxygen=10:0. An oxide conductive film 303 was formed using a film formation gas with a flow rate ratio of argon:oxygen=7:3. An oxide conductive film 304 was formed using a film formation gas with a flow rate ratio of argon:oxygen=5:5. An oxide conductive film 305 was formed using a film formation gas with a flow rate ratio of argon:oxygen=5:5.

As shown in FIGS. 41A and 41B, the etching rate of the oxide conductive film formed under the conditions where the flow rate of argon is higher than the flow rate of oxygen in the film formation is higher than that of the oxide semiconductor film, and thus, the oxide conductive film is processed easily. In the case where the conductive film 112_3 is a metal film such as titanium nitride or tantalum nitride that is commonly used as a barrier metal, dry etching is necessary. In contrast, in the case where an oxide conductive film is used, etching can be performed with a wet etching apparatus as described above, which can process many substrates at a time, is inexpensive, and uses an inexpensive chemical solution.

In the step of forming the conductive films 112 a and 112 b and/or the cleaning step, the thickness of a region of the oxide semiconductor film 108 which is not covered by the conductive films 112 a and 112 b might be reduced.

Then, the insulating films 114 and 116 are formed over the oxide semiconductor film 108 and the conductive films 112 a and 112 b (see FIG. 10).

Note that after the insulating film 114 is formed, the insulating film 116 is preferably formed in succession without exposure to the air. When the insulating film 116 is formed in succession by adjusting at least one of the flow rate of a source gas, pressure, a high-frequency power, and a substrate temperature without exposure to the air after the insulating film 114 is formed, the concentration of impurities attributed to the atmospheric component at the interface between the insulating film 114 and the insulating film 116 can be reduced.

For example, as the insulating film 114, a silicon oxynitride film can be formed by a PECVD method. In this case, a deposition gas including silicon and an oxidizing gas are preferably used as a source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. Examples of the oxidizing gas include dinitrogen monoxide and nitrogen dioxide. The flow rate of the oxidizing gas is more than or equal to 20 times and less than or equal to 5000 times, preferably more than or equal to 40 times and less than or equal to 100 times, that of the deposition gas.

In this embodiment, a silicon oxynitride film is formed as the insulating film 114 by a PECVD method under the conditions where the substrate 102 is held at a temperature of 220° C., silane at a flow rate of 50 sccm and dinitrogen monoxide at a flow rate of 2000 sccm are used as a source gas, the pressure in the treatment chamber is 20 Pa, and a high-frequency power of 100 W at 13.56 MHz (1.6×10⁻² W/cm² as the power density) is supplied to parallel-plate electrodes.

As the insulating film 116, a silicon oxide film or a silicon oxynitride film is formed under the following conditions: the substrate placed in a treatment chamber of the PECVD apparatus that is vacuum-evacuated is held at a temperature higher than or equal to 180° C. and lower than or equal to 350° C.; the pressure is greater than or equal to 100 Pa and less than or equal to 250 Pa, preferably greater than or equal to 100 Pa and less than or equal to 200 Pa with introduction of a source gas into the treatment chamber; and a high-frequency power of greater than or equal to 0.17 W/cm² and less than or equal to 0.5 W/cm², preferably greater than or equal to 0.25 W/cm² and less than or equal to 0.35 W/cm² is supplied to an electrode provided in the treatment chamber.

As the film formation conditions of the insulating film 116, the high-frequency power having the above power density is supplied to a reaction chamber having the above pressure, whereby the degradation efficiency of the source gas in plasma is increased, oxygen radicals are increased, and oxidation of the source gas is promoted; thus, the oxygen content in the insulating film 116 becomes higher than that in the stoichiometric composition. On the other hand, in the film formed at a substrate temperature within the above temperature range, the bond between silicon and oxygen is weak, and accordingly, part of oxygen in the film is released by heat treatment in a later step. Thus, it is possible to form an oxide insulating film which contains oxygen in excess of that in the stoichiometric composition and from which part of oxygen is released by heating.

Note that the insulating film 114 serves as a protection film for the oxide semiconductor film 108 in the step of forming the insulating film 116. Therefore, the insulating film 116 can be formed using the high-frequency power having a high power density while damage to the oxide semiconductor film 108 is reduced.

Note that in the film formation conditions of the insulating film 116, when the flow rate of the deposition gas including silicon with respect to the oxidizing gas is increased, the amount of defects in the insulating film 116 can be reduced. Typically, it is possible to form an oxide insulating film in which the amount of defects is small, that is, the spin density corresponding to a signal which appears at g=2.001 due to a dangling bond of silicon is lower than 6×10¹⁷ spins/cm³, preferably lower than or equal to 3×10¹⁷ spins/cm³, and further preferably lower than or equal to 1.5×10¹⁷ spins/cm³, by ESR measurement. As a result, the reliability of the transistor 100 can be improved.

Heat treatment (hereinafter referred to as second heat treatment) is preferably performed after the insulating films 114 and 116 are formed. The second heat treatment can reduce nitrogen oxide included in the insulating films 114 and 116. By the second heat treatment, part of oxygen contained in the insulating films 114 and 116 can be transferred to the oxide semiconductor film 108, so that the amount of oxygen vacancies included in the oxide semiconductor film 108 can be reduced.

The temperature of the second heat treatment is typically lower than 400° C., preferably lower than 375° C., further preferably higher than or equal to 150° C. and lower than or equal to 350° C. The second heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a rare gas (argon, helium, or the like). Note that an electric furnace, RTA, or the like can be used for the heat treatment, in which it is preferable that hydrogen, water, and the like not be included in the nitrogen, oxygen, ultra-dry air, or a rare gas.

Next, a mask is formed over the insulating film 116 through a lithography process, and the opening portions 152 a and 152 b are formed in desired regions in the insulating films 114 and 116. Note that the opening portion 152 a is formed so as to reach the conductive film 112 b, and the opening portion 152 b is formed so as to reach the conductive film 112 c (see FIG. 11A).

The opening portions 152 a and 152 b can be formed by one or both of a dry etching method and a wet etching method. In this embodiment, the opening portions 152 a and 152 b are formed by a dry etching method.

Then, an oxide conductive film 120_1 and a conductive film 120_2 are formed over the insulating film 116 (see FIG. 11B).

To form the oxide conductive film 120_1, plasma discharge is performed in an atmosphere containing an oxygen gas. At the time, oxygen is added to the insulating film 116 over which the oxide conductive film 120_1 is to be formed. To form the oxide conductive film 120_1, an inert gas (e.g., a helium gas, an argon gas, or a xenon gas) and an oxygen gas may be mixed.

The oxygen gas is mixed at least when the oxide conductive film 120_1 is formed. The proportion of the oxygen gas in a film formation gas for forming the oxide conductive film 120_1 is higher than 0% and lower than or equal to 100%, preferably higher than or equal to 10% and lower than or equal to 100%, more preferably higher than or equal to 30% and lower than or equal to 100%.

In this embodiment, the oxide conductive film 120_1 is formed by a sputtering method using an In—Ga—Zn metal oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]).

Note that although oxygen is added to the insulating film 116 when the oxide conductive film 120_1 is formed in this embodiment, the method for adding oxygen is not limited to this example. For example, oxygen may be further added to the insulating film 116 after the oxide conductive film 120_1 is formed.

As an example of a method for adding oxygen to the insulating film 116, a 5-nm-thick ITSO film is formed using an ITSO target (In₂O₃:SnO₂:SiO₂=85:10:5 [weight %]) as the oxide conductive film 120_1.

In that case, the thickness of the oxide conductive film 120_1 is preferably greater than or equal to 1 nm and less than or equal to 20 nm or greater than or equal to 2 nm and less than or equal to 10 nm, in which case oxygen is favorably transmitted and release of oxygen can be inhibited. Then, oxygen is added to the insulating film 116 through the oxide conductive film 120_1. Oxygen can be added by, for example, ion doping, ion implantation, or plasma treatment. By application of a bias voltage to the substrate side when oxygen is added, oxygen can be effectively added to the insulating film 116. An ashing apparatus is used, for example, and power density of the bias voltage applied to a substrate side of the ashing apparatus can be greater than or equal to 1 W/cm² and less than or equal to 5 W/cm² as the bias voltage. The substrate temperature during addition of oxygen is higher than or equal to room temperature and lower than or equal to 300° C., preferably higher than or equal to 100° C. and lower than or equal to 250° C., whereby oxygen can be added efficiently to the insulating film 116. Note that the oxide conductive film 120_1 may be removed before a subsequent step. In the case where the oxide conductive film 120_1 is an ITSO film, the oxide conductive film 120_1 can be removed using a PAN etchant.

Then, a 100-nm-thick titanium film is formed by a sputtering method as the conductive film 120_2.

After a mask is formed through a lithography method over the conductive film 120_2, the conductive film 120_2 and the oxide conductive film 120_1 are processed into desired shapes, whereby the island-shaped conductive films 120 a and 120 b are formed. Note that the conductive film 120 a includes the island-shaped oxide conductive film 120 a_1 and the island-shaped conductive film 120 a_2, and the conductive film 120 b includes the island-shaped oxide conductive film 120 b_1 and the island-shaped conductive film 120 b_2 (see FIG. 11C).

Then, the insulating film 118 is formed over the insulating film 116 and the conductive films 120 a and 120 b (see FIG. 12).

The insulating film 118 includes one or both of hydrogen and nitrogen. As the insulating film 118, a silicon nitride film is preferably used, for example. The insulating film 118 can be formed by a sputtering method or a PECVD method, for example. In the case where the insulating film 118 is formed by a PECVD method, for example, the substrate temperature is lower than 400° C., preferably lower than 375° C., and further preferably higher than or equal to 180° C. and lower than or equal to 350° C. The substrate temperature at which the insulating film 118 is formed is preferably within the above range because a dense film can be formed. Furthermore, when the substrate temperature at which the insulating film 118 is formed is within the above range, oxygen or excess oxygen in the insulating films 114 and 116 can be moved to the oxide semiconductor film 108.

In the case where a silicon nitride film is formed by a PECVD method as the insulating film 118, a deposition gas containing silicon, nitrogen, and ammonia are preferably used as a source gas. A small amount of ammonia compared with the amount of nitrogen is used, whereby ammonia is dissociated in the plasma and activated species are generated. The activated species cleave a bond between silicon and hydrogen which are included in a deposition gas including silicon and a triple bond between nitrogen molecules. As a result, a dense silicon nitride film having few defects, in which bonds between silicon and nitrogen are promoted and bonds between silicon and hydrogen are few, can be formed. On the other hand, when the amount of ammonia with respect to nitrogen is large, decomposition of a deposition gas including silicon and decomposition of nitrogen are not promoted, so that a sparse silicon nitride film in which bonds between silicon and hydrogen remain and defects are increased is formed. Therefore, in the source gas, the flow rate of nitrogen is set to be preferably 5 times or more and 50 times or less, more preferably 10 times or more and 50 times or less the flow rate of ammonia.

In this embodiment, with the use of a PECVD apparatus, a 50-nm-thick silicon nitride film is formed as the insulating film 118 using silane, nitrogen, and ammonia as a source gas. The flow rate of silane is 50 sccm, the flow rate of nitrogen is 5000 sccm, and the flow rate of ammonia is 100 sccm. The pressure in the treatment chamber is 100 Pa, the substrate temperature is 350° C., and high-frequency power of 1000 W is supplied to parallel-plate electrodes with a 27.12 MHz high-frequency power source. Note that the PECVD apparatus is a parallel-plate PECVD apparatus in which the electrode area is 6000 cm², and the power per unit area (power density) into which the supplied power is converted is 1.7×10⁻¹ W/cm².

After the insulating film 118 is formed, heat treatment similar to the first heat treatment or the second heat treatment (hereinafter referred to as third heat treatment) may be performed.

By the third heat treatment, oxygen that is added to the insulating film 116 in forming the oxide conductive film 120_1 is moved to the oxide semiconductor film 108 (in particular, the oxide semiconductor film 108 b) and fills oxygen vacancy in the oxide semiconductor film 108.

Through the above process, the transistor 100 illustrated in FIGS. 1A to 1C can be manufactured.

In the entire manufacturing process of the transistor 100, the substrate temperature is preferably lower than 400° C., further preferably lower than 375° C., still further preferably higher than or equal to 180° C. and lower than or equal to 350° C. because the change in shape of the substrate (distortion or warp) can be reduced even when a large-sized substrate is used. As typical examples of a step in which the substrate temperature is increased in the manufacturing process of the transistor 100, the following are given: the substrate temperature in the formation of the insulating films 106 and 107 (lower than 400° C., preferably higher than or equal to 250° C. and lower than or equal to 350° C.), the substrate temperature in the formation of the oxide semiconductor film 108 (higher than or equal to room temperature and lower than 340° C., preferably higher than or equal to 100° C. and lower than or equal to 200° C., further preferably higher than or equal to 100° C. and lower than 150° C.), the substrate temperature in the formation of the insulating films 116 and 118 (lower than 400° C., preferably lower than 375° C., further preferably higher than or equal to 180° C. and lower than or equal to 350° C.), and the first heat treatment, the second heat treatment, or the third heat treatment (lower than 400° C., preferably lower than 375° C., further preferably higher than or equal to 180° C. and lower than or equal to 350° C.).

Note that the structure and method described in this embodiment can be used in appropriate combination with the structure and method described in any of the other embodiments.

Embodiment 2

In this embodiment, the composition, the structure, and the like of an oxide semiconductor that can be used in one embodiment of the present invention are described with reference to FIGS. 13A to 13C, FIG. 14, FIGS. 15A and 15B, FIGS. 16A to 16E, FIGS. 17A to 17E, FIGS. 18A to 18D, FIGS. 19A and 19B, and FIG. 20.

<2-1. Composition of Oxide Semiconductor>

Composition of an oxide semiconductor is described below. Note that in this embodiment, an oxide semiconductor is also simply referred to as an oxide to describe its composition.

An oxide preferably contains at least indium or zinc. In particular, indium and zinc are preferably contained. In addition, aluminum, gallium, yttrium, tin, or the like is preferably contained. Furthermore, one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be contained.

Here, the case where an oxide contains indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Alternatively, the element M can be boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. Note that two or more of the above elements may be used in combination as the element M.

First, preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide according to the present invention are described with reference to FIGS. 13A to 13C. Note that the proportion of oxygen atoms is not shown in FIGS. 13A to 13C. The terms of the atomic ratio of indium, the element M, and zinc contained in the oxide are denoted by [In], [M], and [Zn], respectively.

In FIGS. 13A to 13C, broken lines indicate a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):1, where −1≤α≤1, a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):2, a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):3, a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):4, and a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):5.

Dashed-dotted lines indicate a line where the atomic ratio [In]:[M]:[Zn] is 1:1:β, where β≥0, a line where the atomic ratio [In]:[M]:[Zn] is 1:2:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:3:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:4:β, a line where the atomic ratio [In]:[M]:[Zn] is 2:1:β, and a line where the atomic ratio [In]:[M]:[Zn] is 5:1:β.

An oxide having the atomic ratio of [In]:[M]:[Zn]=0:2:1 or a neighborhood thereof in FIGS. 13A to 13C tends to have a spinel crystal structure.

FIGS. 13A and 13B show examples of the preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide in one embodiment of the present invention.

FIG. 14 shows an example of the crystal structure of InMZnO₄ whose atomic ratio [In]:[M]:[Zn] is 1:1:1. The crystal structure shown in FIG. 14 is InMZnO₄ observed from a direction parallel to a b-axis. Note that a metal element in a layer that contains M, Zn, and oxygen (hereinafter, this layer is referred to as an “(M,Zn) layer”) in FIG. 14 represents the element M or zinc. In that case, the proportion of the element M is the same as the proportion of zinc. The element M and zinc can be replaced with each other, and their arrangement is random.

InMZnO₄ has a layered crystal structure (also referred to as a layered structure) and includes one layer that contains indium and oxygen (hereinafter referred to as an In layer) for every two (M,Zn) layers that contain the element M, zinc, and oxygen, as shown in FIG. 14.

Indium and the element M can be replaced with each other. Therefore, when the element M in the (M,Zn) layer is replaced with indium, the layer can also be referred to as an (In,M,Zn) layer. In that case, a layered structure that contains one In layer for every two (In,M,Zn) layers is obtained.

An oxide whose atomic ratio [In]:[M]:[Zn] is 1:1:2 has a layered structure that contains one In layer for every three (M,Zn) layers. In other words, if [Zn] is higher than [In] and [M], the proportion of the (M,Zn) layer to the In layer becomes higher when the oxide is crystallized.

Note that in the case where the number of (M,Zn) layers with respect to one In layer is not an integer in the oxide, the oxide might have plural kinds of layered structures where the number of (M,Zn) layers with respect to one In layer is an integer. For example, in the case of [In]:[M]:[Zn]=1:1:1.5, the oxide might have the following layered structures: a layered structure of one In layer for every two (M,Zn) layers and a layered structure of one In layer for every three (M,Zn) layers.

For example, in the case where the oxide is deposited with a sputtering apparatus, a film having an atomic ratio deviated from the atomic ratio of a target is formed. In particular, [Zn] in the film might be smaller than [Zn] in the target depending on the substrate temperature in deposition.

A plurality of phases (e.g., two phases or three phases) exist in the oxide in some cases. For example, with an atomic ratio [In]:[M]:[Zn] that is close to 0:2:1, two phases of a spinel crystal structure and a layered crystal structure are likely to exist. In addition, with an atomic ratio [In]:[M]:[Zn] that is close to 1:0:0, two phases of a bixbyite crystal structure and a layered crystal structure are likely to exist. In the case where a plurality of phases exist in the oxide, a grain boundary might be formed between different crystal structures.

In addition, the oxide containing indium in a higher proportion can have high carrier mobility (electron mobility). Therefore, an oxide having a high content of indium has higher carrier mobility than an oxide having a low content of indium.

In contrast, when the indium content and the zinc content in an oxide become lower, carrier mobility becomes lower. Thus, with an atomic ratio of [In]:[M]:[Zn]=0:1:0 and the vicinity thereof (e.g., a region C in FIG. 13C), insulation performance becomes better.

Accordingly, an oxide in one embodiment of the present invention preferably has an atomic ratio represented by a region A in FIG. 13A. With the atomic ratio, a layered structure with high carrier mobility and a few grain boundaries is easily obtained.

A region B in FIG. 13B represents an atomic ratio of [In]:[M]:[Zn]=4:2:3 to 4:2:4.1 and the vicinity thereof. The vicinity includes an atomic ratio of [In]:[M]:[Zn]=5:3:4. An oxide with an atomic ratio represented by the region B is an excellent oxide that has particularly high crystallinity and high carrier mobility.

Note that a condition where an oxide forms a layered structure is not uniquely determined by an atomic ratio. There is a difference in the degree of difficulty in forming a layered structure among atomic ratios. Even with the same atomic ratio, whether a layered structure is formed or not depends on a formation condition. Therefore, the illustrated regions each represent an atomic ratio with which an oxide has a layered structure, and boundaries of the regions A to C are not clear.

Next, the case where the oxide is used for a transistor is described.

Note that when the oxide is used for a transistor, carrier scattering or the like at a grain boundary can be reduced; thus, the transistor can have high field-effect mobility. In addition, the transistor can have high reliability.

An oxide with low carrier density is preferably used for the transistor. For example, an oxide whose carrier density is lower than 8×10¹¹/cm³, preferably lower than 1×10¹¹/cm³, more preferably lower than 1×10¹⁰/cm³, and greater than or equal to 1×10⁹/cm³ is used.

A highly purified intrinsic or substantially highly purified intrinsic oxide has few carrier generation sources and thus can have a low carrier density. The highly purified intrinsic or substantially highly purified intrinsic oxide has a low density of defect states and accordingly has a low density of trap states in some cases.

Charge trapped by the trap states in the oxide takes a long time to be released and may behave like fixed charge. Thus, a transistor whose channel region is formed in an oxide having a high density of trap states has unstable electrical characteristics in some cases.

In order to obtain stable electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the oxide. In addition, in order to reduce the concentration of impurities in the oxide, the concentration of impurities in a film that is adjacent to the oxide is preferably reduced. Examples of impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, and silicon.

Here, the influence of impurities in the oxide is described.

When silicon or carbon that is one of Group 14 elements is contained in the oxide, defect states are formed. Thus, the concentration of silicon or carbon in the oxide and around an interface with the oxide (measured by secondary ion mass spectrometry (SIMS)) is set lower than or equal to 2×10¹⁸ atoms/cm³, and preferably lower than or equal to 2×10¹⁷ atoms/cm³.

When the oxide contains alkali metal or alkaline earth metal, defect states are formed and carriers are generated, in some cases. Thus, a transistor including an oxide that contains alkali metal or alkaline earth metal is likely to be normally-on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide. Specifically, the concentration of alkali metal or alkaline earth metal of the oxide, which is measured by SIMS, is set lower than or equal to 1×10¹⁸ atoms/cm³, and preferably lower than or equal to 2×10¹⁶ atoms/cm³.

When the oxide contains nitrogen, the oxide easily becomes n-type by generation of electrons serving as carriers and an increase of carrier density. Thus, a transistor whose semiconductor includes an oxide that contains nitrogen is likely to be normally-on. For this reason, nitrogen in the oxide is preferably reduced as much as possible; the nitrogen concentration of the oxide, which is measured by SIMS, is set, for example, lower than 5×10¹⁹ atoms/cm³, preferably lower than or equal to 5×10¹⁸ atoms/cm³, further preferably lower than or equal to 1×10¹⁸ atoms/cm³, and still further preferably lower than or equal to 5×10¹⁷ atoms/cm³.

Hydrogen contained in an oxide reacts with oxygen bonded to a metal atom to be water, and thus causes an oxygen vacancy, in some cases. Due to entry of hydrogen into the oxygen vacancy, an electron serving as a carrier is generated in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, a transistor including an oxide that contains hydrogen is likely to be normally-on. Accordingly, it is preferable that hydrogen in the oxide be reduced as much as possible. Specifically, the hydrogen concentration of the oxide, which is measured by SIMS, is set lower than 1×10²⁰ atoms/cm³, preferably lower than 1×10¹⁹ atoms/cm³, further preferably lower than 5×10¹⁸ atoms/cm³, and still further preferably lower than 1×10¹⁸ atoms/cm³.

When an oxide with sufficiently reduced impurity concentration is used for a channel formation region in a transistor, the transistor can have stable electrical characteristics.

<2-2. Stacked-Layer Structure of Oxide Semiconductor>

Next, a stacked-layer structure of an oxide semiconductor is described.

Here, as a stacked-layer structure of an oxide semiconductor, the case where the oxide semiconductor has a two-layer structure or a three-layer structure is described. FIGS. 15A and 15B are a band diagram of a stacked-layer structure of an oxide semiconductor S1, an oxide semiconductor S2, and an oxide semiconductor S3 and insulators in contact with the stacked-layer structure and a band diagram of a stacked-layer structure of the oxide semiconductor S2 and the oxide semiconductor S3 and insulators in contact with the stacked-layer structure.

FIG. 15A is an example of a band diagram of a stacked-layer structure including an insulator I1, the oxide semiconductor S1 the oxide semiconductor S2, the oxide semiconductor S3, and an insulator I2 in a film thickness direction. FIG. 15B is an example of a band diagram of a stacked-layer structure including the insulator I1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator I2 in a film thickness direction. Note that for easy understanding, the band diagrams show the energy level of the conduction band minimum (Ec) of each of the insulator I1, the oxide semiconductor S1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator I2.

The energy level of the conduction band minimum of each of the oxide semiconductors S1 and S3 is closer to the vacuum level than that of the oxide semiconductor S2. Typically, a difference in energy level between the conduction band minimum of the oxide semiconductor S2 and the conduction band minimum of each of the oxide semiconductors S1 and S3 is preferably greater than or equal to 0.15 eV or greater than or equal to 0.5 eV, and less than or equal to 2 eV or less than or equal to 1 eV. That is, it is preferable that the electron affinity of the oxide semiconductor S2 be higher than the electron affinity of each of the oxide semiconductors S1 and S3, and the difference between the electron affinity of each of the oxide semiconductors S1 and S3 and the electron affinity of the oxide semiconductor S2 be greater than or equal to 0.15 eV or greater than or equal to 0.5 eV, and less than or equal to 2 eV or less than or equal to 1 eV.

As shown in FIGS. 15A and 15B, the energy level of the conduction band minimum of each of the oxide semiconductors S1 to S3 is gradually varied. In other words, the energy level of the conduction band minimum is continuously varied or continuously connected. In order to obtain such a band diagram, the density of defect states in a mixed layer formed at an interface between the oxide semiconductors S1 and S2 or an interface between the oxide semiconductors S2 and S3 is preferably made low.

Specifically, when the oxide semiconductors S1 and S2 or the oxide semiconductors S2 and S3 contain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide semiconductor S2 is an In—Ga—Zn oxide semiconductor, it is preferable to use an In—Ga—Zn oxide semiconductor, a Ga—Zn oxide semiconductor, gallium oxide, or the like as each of the oxide semiconductors S1 and S3.

At this time, the oxide semiconductor S2 serves as a main carrier path. Since the density of defect states at the interface between the oxide semiconductors S1 and S2 and the interface between the oxide semiconductors S2 and S3 can be made low, the influence of interface scattering on carrier conduction is small, and high on-state current can be obtained.

When an electron is trapped in a trap state, the trapped electron behaves like fixed charge; thus, the threshold voltage of the transistor is shifted in a positive direction. The oxide semiconductors S1 and S3 can make the trap state apart from the oxide semiconductor S2. This structure can prevent the positive shift of the threshold voltage of the transistor.

A material whose conductivity is sufficiently lower than that of the oxide semiconductor S2 is used for the oxide semiconductors S1 and S3. In that case, the oxide semiconductor S2, the interface between the oxide semiconductors S1 and S2, and the interface between the oxide semiconductors S2 and S3 mainly function as a channel region. For example, an oxide semiconductor with high insulation performance and the atomic ratio represented by the region C in FIG. 13C can be used as the oxide semiconductors S1 and S3. Note that the region C in FIG. 13C represents the atomic ratio of [In]:[M]:[Zn]=0:1:0 and the vicinity thereof.

In the case where an oxide semiconductor with the atomic ratio represented by the region A is used as the oxide semiconductor S2, it is particularly preferable to use an oxide semiconductor with an atomic ratio [M]/[In] that is greater than or equal to 1, preferably greater than or equal to 2 as each of the oxide semiconductors S1 and S3. In addition, it is suitable to use an oxide semiconductor with an atomic ratio [M]/([Zn]+[In]) that is greater than or equal to 1, which has sufficiently high insulation performance, as the oxide semiconductor S3.

<2-3. Structure of Oxide Semiconductor>

Next, a structure of an oxide semiconductor is described.

An oxide semiconductor is classified into a single-crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.

From another perspective, an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of the crystalline oxide semiconductor include a single-crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

An amorphous structure is generally thought to be isotropic and have no non-uniform structure, to be metastable and have no fixed atomic arrangement, to have a flexible bond angle, and to have a short-range order but have no long-range order, for example.

In other words, a stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Moreover, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that has a periodic structure in a microscopic region) cannot be regarded as a completely amorphous oxide semiconductor. In contrast, an a-like OS, which is not isotropic, has an unstable structure that includes a void. Because of its instability, an a-like OS has physical properties similar to those of an amorphous oxide semiconductor.

[CAAC-OS]

First, a CAAC-OS is described.

A CAAC-OS is one of oxide semiconductors and has a plurality of c-axis aligned crystal parts (also referred to as pellets).

Analysis of a CAAC-OS by X-ray diffraction (XRD) is described. For example, when the structure of a CAAC-OS including an InGaZnO₄ crystal, which is classified into the space group R-3m, is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as shown in FIG. 16A. This peak is derived from the (009) plane of the InGaZnO₄ crystal, which indicates that crystals in the CAAC-OS have c-axis alignment and that the c-axes are aligned in the direction substantially perpendicular to a surface over which the CAAC-OS is formed (also referred to as a formation surface) or a top surface of the CAAC-OS. Note that a peak sometimes appears at 2θ of around 36° in addition to the peak at 2θ of around 31°. The peak at 2θ of around 36° is attributed to a crystal structure classified into the space group Fd-3m; thus, this peak is preferably not exhibited in the CAAC-OS.

On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray is incident on the CAAC-OS in the direction parallel to the formation surface, a peak appears at 2θ of around 56°. This peak is derived from the (110) plane of the InGaZnO₄ crystal. When analysis (ϕ scan) is performed with 2θ fixed at around 56° while the sample is rotated around a normal vector to the sample surface as an axis (ϕ axis), as shown in FIG. 16B, a peak is not clearly observed. In contrast, in the case where single-crystal InGaZnO₄ is subjected to ϕ scan with 2θ fixed at around 56°, as shown in FIG. 16C, six peaks that are derived from crystal planes equivalent to the (110) plane are observed. Accordingly, the structural analysis using XRD shows that the directions of the a-axes and b-axes are irregularly oriented in the CAAC-OS.

Next, a CAAC-OS analyzed by electron diffraction is described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO₄ crystal in the direction parallel to the formation surface of the CAAC-OS, a diffraction pattern (also referred to as a selected-area electron diffraction pattern) in FIG. 16D can be obtained. This diffraction pattern includes spots derived from the (009) plane of the InGaZnO₄ crystal. Thus, the results of electron diffraction also indicate that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in the direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile, FIG. 16E shows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in the direction perpendicular to the sample surface. In FIG. 16E, a ring-like diffraction pattern is observed. Thus, the results of electron diffraction using an electron beam with a probe diameter of 300 nm also indicate that the a-axes and b-axes of the pellets included in the CAAC-OS do not have regular alignment. The first ring in FIG. 16E is considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO₄ crystal. The second ring in FIG. 16E is considered to be derived from the (110) plane and the like.

In a combined analysis image (also referred to as a high-resolution transmission electron microscope (TEM) image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a TEM, a plurality of pellets can be observed. However, even in the high-resolution TEM image, a boundary between pellets, that is, a grain boundary is not clearly observed in some cases. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur.

FIG. 17A shows a high-resolution TEM image of a cross section of the CAAC-OS that is observed in the direction substantially parallel to the sample surface. The high-resolution TEM image is obtained with a spherical aberration corrector function. The high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 17A shows pellets in which metal atoms are arranged in a layered manner. FIG. 17A proves that the size of a pellet is greater than or equal to 1 nm or greater than or equal to 3 nm. Thus, the pellet can also be referred to as a nanocrystal (nc). Furthermore, the CAAC-OS can also be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC). A pellet reflects unevenness of a formation surface or a top surface of the CAAC-OS and is parallel to the formation surface or the top surface of the CAAC-OS.

FIGS. 17B and 17C show Cs-corrected high-resolution TEM images of a plane of the CAAC-OS observed in the direction substantially perpendicular to the sample surface. FIGS. 17D and 17E are images obtained by image processing of FIGS. 17B and 17C. The method of image processing is as follows. The image in FIG. 17B is subjected to fast Fourier transform (FFT) to obtain an FFT image. Then, mask processing is performed on the obtained FFT image such that part in the range of 2.8 nm⁻¹ to 5.0 nm⁻¹ from the reference point is left. After the mask processing, the FFT image is subjected to inverse fast Fourier transform (IFFT) to obtain a processed image. The image obtained in this manner is referred to as an FFT filtering image. The FFT filtering image is a Cs-corrected high-resolution TEM image from which a periodic component is extracted and shows a lattice arrangement.

In FIG. 17D, a portion in which the lattice arrangement is broken is shown by dashed lines. A region surrounded by dashed lines corresponds to one pellet. The portion denoted by the dashed lines is a junction of pellets. The dashed lines draw a hexagon, which means that the pellet has a hexagonal shape. Note that the shape of the pellet is not always a regular hexagon but is a non-regular hexagon in many cases.

In FIG. 17E, a dotted line denotes a portion where the direction of a lattice arrangement changes between a region with a regular lattice arrangement and another region with a regular lattice arrangement, and a dashed line denotes the change in the direction of the lattice arrangement. A clear crystal grain boundary cannot be observed even in the vicinity of the dotted line. When a lattice point in the vicinity of the dotted line is regarded as a center and surrounding lattice points are joined, a distorted hexagon, a distorted pentagon, and/or a distorted heptagon can be formed, for example. That is, a lattice arrangement is distorted so that formation of a crystal grain boundary is inhibited. This is probably because the CAAC-OS can tolerate distortion owing to a low density of arrangement of oxygen atoms in an a-b plane direction, the interatomic bond distance changed by substitution of a metal element, and the like.

As described above, the CAAC-OS has c-axis alignment, its pellets (nanocrystals) are connected in the a-b plane direction, and its crystal structure has distortion. For this reason, the CAAC-OS can also be referred to as an oxide semiconductor including a c-axis-aligned a-b-plane-anchored (CAA) crystal.

The CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has few impurities and defects (e.g., oxygen vacancies).

Note that an impurity means an element other than the main components of an oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (e.g., silicon) having stronger bonding force to oxygen than a metal element constituting a part of an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in a disordered atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

The characteristics of an oxide semiconductor having impurities or defects might be changed by light, heat, or the like. For example, impurities contained in the oxide semiconductor might serve as carrier traps or carrier generation sources. For example, oxygen vacancy in the oxide semiconductor might serve as a carrier trap or serve as a carrier generation source when hydrogen is captured therein.

The CAAC-OS having small amounts of impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, an oxide semiconductor with a carrier density of lower than 8×10¹¹/cm³, preferably lower than 1×10¹¹/cm³, further preferably lower than 1×10¹⁰/cm³, and higher than or equal to 1×10⁻⁹/cm³ can be used. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. A CAAC-OS has a low impurity concentration and a low density of defect states. Thus, the CAAC-OS can be referred to as an oxide semiconductor having stable characteristics.

[nc-OS]

Next, an nc-OS is described.

Analysis of an nc-OS by XRD is described. When the structure of an nc-OS is analyzed by an out-of-plane method, a peak indicating orientation does not appear. That is, a crystal of an nc-OS does not have orientation.

For example, when an electron beam with a probe diameter of 50 nm is incident on a 34-nm-thick region of a thinned nc-OS including an InGaZnO₄ crystal in the direction parallel to the formation surface, a ring-like diffraction pattern (nanobeam electron diffraction pattern) shown in FIG. 18A is observed. FIG. 18B shows a diffraction pattern (nanobeam electron diffraction pattern) obtained when an electron beam with a probe diameter of 1 nm is incident on the same sample. In FIG. 18B, a plurality of spots are observed in a ring-like region. Thus, ordering in an nc-OS is not observed with an electron beam with a probe diameter of 50 nm but is observed with an electron beam with a probe diameter of 1 nm.

When an electron beam with a probe diameter of 1 nm is incident on a region with a thickness less than 10 nm, an electron diffraction pattern in which spots are arranged in an approximately regular hexagonal shape as shown in FIG. 18C is observed in some cases. This means that an nc-OS has a well-ordered region, that is, a crystal, in the thickness range of less than 10 nm. Note that an electron diffraction pattern having regularity is not observed in some regions because crystals are aligned in various directions.

FIG. 18D shows a Cs-corrected high-resolution TEM image of a cross section of an nc-OS observed in the direction substantially parallel to the formation surface. In the high-resolution TEM image, the nc-OS has a region in which a crystal part is observed as indicated by additional lines and a region in which a crystal part is not clearly observed. In most cases, the size of a crystal part included in the nc-OS is greater than or equal to 1 nm and less than or equal to 10 nm, specifically greater than or equal to 1 nm and less than or equal to 3 nm. Note that an oxide semiconductor including a crystal part whose size is greater than 10 nm and less than or equal to 100 nm may be referred to as a microcrystalline oxide semiconductor. In a high-resolution TEM image of the nc-OS, for example, a grain boundary is not clearly observed in some cases. Note that there is a possibility that the origin of the nanocrystal is the same as that of a pellet in a CAAC-OS. Thus, a crystal part of the nc-OS may be referred to as a pellet in the following description.

As described above, in the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not observed. Accordingly, in some cases, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method.

Since there is no regularity of crystal orientation between the pellets (nanocrystals), the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC).

The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Thus, the nc-OS has a lower density of defect states than the a-like OS and the amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[a-like OS]

An a-like OS has a structure between the structure of an nc-OS and the structure of an amorphous oxide semiconductor.

FIGS. 19A and 19B show high-resolution cross-sectional TEM images of an a-like OS. The high-resolution cross-sectional TEM image of the a-like OS in FIG. 19A is taken at the start of the electron irradiation. The high-resolution cross-sectional TEM image of the a-like OS in FIG. 19B is taken after the irradiation with electrons (e⁻) at 4.3×10⁸ e⁻/nm². FIGS. 19A and 19B show that striped bright regions extending vertically are observed in the a-like OS from the start of the electron irradiation. It can be also found that the shape of the bright region changes after the electron irradiation. Note that the bright region is presumably a void or a low-density region.

The a-like OS has an unstable structure because it includes a void. To verify that an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation is described below.

An a-like OS, an nc-OS, and a CAAC-OS are prepared as samples. Each of the samples is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts.

It is known that a unit cell of an InGaZnO₄ crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. The distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion in which the spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO₄ in the following description. Each lattice fringe corresponds to the a-b plane of the InGaZnO₄ crystal.

FIG. 20 shows a change in the average size of crystal parts (at 22 points to 30 points) in each sample. Note that the crystal part size corresponds to the length of a lattice fringe. FIG. 20 indicates that the crystal part size in the a-like OS increases with an increase in the cumulative electron dose in obtaining TEM images, for example. As shown in FIG. 20, a crystal part with a size of approximately 1.2 nm (also referred to as an initial nucleus) at the start of TEM observation grows to a size of approximately 1.9 nm at a cumulative electron (e) dose of 4.2×10⁸ e⁻/nm². In contrast, the crystal part sizes in the nc-OS and the CAAC-OS show few changes from the start of electron irradiation to a cumulative electron dose of 4.2×10⁸ e⁻/nm². As shown in FIG. 20, the crystal part sizes in the nc-OS and the CAAC-OS are approximately 1.3 nm and approximately 1.8 nm, respectively, regardless of the cumulative electron dose. For the electron beam irradiation and TEM observation, a Hitachi H-9000NAR transmission electron microscope was used. The conditions of the electron beam irradiation were as follows: the accelerating voltage was 300 kV; the current density was 6.7×10⁵ e⁻/(nm²·s); and the diameter of an irradiation region was 230 nm.

In this manner, growth of the crystal part in the a-like OS may be induced by electron irradiation. In contrast, in the nc-OS and the CAAC-OS, growth of the crystal part is hardly induced by electron irradiation. That is, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

The a-like OS has a lower density than the nc-OS and the CAAC-OS because it includes a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single-crystal oxide semiconductor having the same composition. The density of the nc-OS and the density of the CAAC-OS are each higher than or equal to 92.3% and lower than 100% of the density of the single-crystal oxide semiconductor having the same composition. It is difficult to deposit an oxide semiconductor having a density lower than 78% of the density of the single-crystal oxide semiconductor.

For example, in the case of an oxide semiconductor whose atomic ratio of In to Ga and Zn is 1:1:1, the density of single-crystal InGaZnO₄ with a rhombohedral crystal structure is 6.357 g/cm³. Accordingly, in the case of the oxide semiconductor whose atomic ratio of In to Ga and Zn is 1:1:1, the density of the a-like OS is higher than or equal to 5.0 g/cm³ and lower than 5.9 g/cm³, for example. In the case of the oxide semiconductor whose atomic ratio of In to Ga and Zn is 1:1:1, the density of the nc-OS and the density of the CAAC-OS are each higher than or equal to 5.9 g/cm³ and lower than 6.3 g/cm³, for example.

In the case where an oxide semiconductor having a certain composition does not exist in a single-crystal state, single-crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to calculate a density equivalent to that of a single-crystal oxide semiconductor with the desired composition. The density of a single-crystal oxide semiconductor having the desired composition may be calculated using a weighted average with respect to the combination ratio of the single-crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single-crystal oxide semiconductors as possible to calculate the density.

As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

The structures described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

Embodiment 3

In this embodiment, an example of a display device that includes the transistor described in the above embodiments is described below with reference to FIG. 21 to FIG. 27.

FIG. 21 is a top view illustrating an example of a display device. A display device 700 in FIG. 21 includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 that are provided over the first substrate 701, a sealant 712 provided to surround the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, and a second substrate 705 provided to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with the sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are enclosed by the first substrate 701, the sealant 712, and the second substrate 705. Although not illustrated in FIG. 21, a display element is provided between the first substrate 701 and the second substrate 705.

In the display device 700, a flexible printed circuit (FPC) terminal portion 708 that is electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 is provided in a region different from the region that is over the first substrate 701 and surrounded by the sealant 712. Furthermore, an FPC 716 is connected to the FPC terminal portion 708, and a variety of signals and the like are supplied from the FPC 716 to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706. Furthermore, a signal line 710 is connected to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708. Through the signal line 710, a variety of signals and the like are supplied from the FPC 716 to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708.

A plurality of gate driver circuit portions 706 may be provided in the display device 700. The structure of the display device 700 is not limited to the example shown here, in which the source driver circuit portion 704 and the gate driver circuit portion 706 as well as the pixel portion 702 are formed over the first substrate 701. For example, only the gate driver circuit portion 706 may be formed over the first substrate 701, or only the source driver circuit portion 704 may be formed over the first substrate 701. In this case, a substrate over which a source driver circuit, a gate driver circuit, or the like is formed (e.g., a driver circuit board formed using a single-crystal semiconductor film or a polycrystalline semiconductor film) may be formed on the first substrate 701. Note that there is no particular limitation on the method for connecting the separately prepared driver circuit board, and a chip on glass (COG) method, a wire bonding method, or the like can be used.

The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 include a plurality of transistors. As the plurality of transistors, any of the transistors that are semiconductor devices of embodiments of the present invention can be used.

The display device 700 can include a variety of elements. As examples of the elements, electroluminescent (EL) element (e.g., an EL element containing organic and inorganic materials, an organic EL element, an inorganic EL element, or an LED), a light-emitting transistor element (a transistor that emits light depending on current), an electron emitter, a liquid crystal element, an electronic ink display, an electrophoretic element, an electrowetting element, a plasma display panel (PDP), a micro electro mechanical systems (MEMS) display (e.g., a grating light valve (GLV), a digital micromirror device (DMD), or a digital micro shutter (DMS) element), an interferometric modulator display (IMOD), and a piezoelectric ceramic display can be given.

An example of a display device including an EL element is an EL display. Examples of a display device including an electron emitter include a field emission display (FED) and an SED-type flat panel display (SED: surface-conduction electron-emitter display). An example of a display device including a liquid crystal element is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display). An example of a display device including an electronic ink display or an electrophoretic element is electronic paper. In a transflective liquid crystal display or a reflective liquid crystal display, some or all of pixel electrodes may function as reflective electrodes. For example, some or all of pixel electrodes may contain aluminum, silver, or the like. In this case, a memory circuit such as an SRAM can be provided under the reflective electrodes, leading to lower power consumption.

As a display system of the display device 700, a progressive system, an interlace system, or the like can be employed. Furthermore, color elements controlled in pixels at the time of color display are not limited to three colors: R, G, and B (R, G, and B correspond to red, green, and blue, respectively). For example, four pixels of an R pixel, a G pixel, a B pixel, and a W (white) pixel may be used. Alternatively, a color element may be composed of two colors of R, G, and B as in PenTile layout. The two colors may differ between color elements. Alternatively, one or more colors of yellow, cyan, magenta, and the like may be added to RGB. Note that the size of a display region may differ between dots of color elements. One embodiment of the disclosed invention is not limited to a color display device; the disclosed invention can also be applied to a monochrome display device.

A coloring layer (also referred to as a color filter) may be used to obtain a full-color display device in which white light (W) is used for a backlight (e.g., an organic EL element, an inorganic EL element, an LED, or a fluorescent lamp). For example, a red (R) coloring layer, a green (G) coloring layer, a blue (B) coloring layer, and a yellow (Y) coloring layer can be combined as appropriate. With the use of the coloring layer, high color reproducibility can be obtained as compared with the case without the coloring layer. Here, by providing a region with a coloring layer and a region without a coloring layer, white light in the region without the coloring layer may be directly utilized for display. By partly providing the region without a coloring layer, a decrease in the luminance of a bright image due to the coloring layer can be suppressed, and approximately 20% to 30% of power consumption can be reduced in some cases. In the case where full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, elements may emit light in their respective colors R, G, B, Y, and W. By using a self-luminous element, power consumption may be further reduced as compared with the case of using a coloring layer.

As a coloring system, any of the following systems may be used: the above-described color filter system in which part of white light is converted into red light, green light, and blue light through color filters; a three-color system in which red light, green light, and blue light are used; and a color conversion system or a quantum dot system in which part of blue light is converted into red light or green light.

In this embodiment, a structure including a liquid crystal element as a display element and a structure including an EL element as a display element are described with reference to FIG. 22 and FIG. 24. FIG. 22 is a cross-sectional view taken along dashed-dotted line Q-R in FIG. 21 and illustrates the structure including a liquid crystal element as a display element. FIG. 24 is a cross-sectional view taken along dashed-dotted line Q-R in FIG. 21 and illustrates the structure including an EL element as a display element.

Portions common to FIG. 22 and FIG. 24 are described first, and then, different portions are described.

<3-1. Portions Common to Display Devices>

The display device 700 in FIG. 22 and FIG. 24 includes a lead wiring portion 711, the pixel portion 702, the source driver circuit portion 704, and the FPC terminal portion 708. The lead wiring portion 711 includes the signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752.

The transistor 750 and the transistor 752 each have a structure similar to that of the transistor 100 described above. Note that the transistor 750 and the transistor 752 may each have the structure of any of the other transistors described in the above embodiments.

The transistor used in this embodiment includes an oxide semiconductor film that is highly purified and in which formation of an oxygen vacancy is suppressed. The transistor can have low off-state current. Accordingly, an electrical signal such as an image signal can be held for a long time, and a long writing interval can be set in an on state. Accordingly, the frequency of refresh operation can be reduced, which suppresses power consumption.

In addition, the transistor used in this embodiment can have relatively high field-effect mobility and thus is capable of high-speed operation. For example, in a liquid crystal display device that includes such a transistor capable of high-speed operation, a switching transistor in a pixel portion and a driver transistor in a driver circuit portion can be formed over one substrate. That is, no additional semiconductor device formed using a silicon wafer or the like is needed as a driver circuit; therefore, the number of components of the semiconductor device can be reduced. In addition, by using the transistor capable of high-speed operation in the pixel portion, a high-quality image can be provided.

The capacitor 790 includes a lower electrode and an upper electrode. The lower electrode is formed through a step of processing the same oxide conductive film as that used for forming the conductive film serving as a first gate electrode included in the transistor 750. The upper electrode is formed through a step of processing the same conductive film as that used for forming a conductive film functioning as a source electrode or a drain electrode of the transistor 750. Between the lower electrode and the upper electrode, an insulating film formed through a step of forming the same insulating film as an insulating film serving as a first gate insulating film included in the transistor 750 is provided. That is, the capacitor 790 has a stacked-layer structure in which the insulating films functioning as a dielectric film are positioned between the pair of electrodes.

In FIG. 22 and FIG. 24, a planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.

The planarization insulating film 770 can be formed using a heat-resistant organic material such as a polyimide resin, an acrylic resin, a polyimide amide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin. Note that the planarization insulating film 770 may be formed by stacking a plurality of insulating films formed using any of these materials. A structure without the planarization insulating film 770 may also be employed.

Although FIG. 22 and FIG. 24 each illustrate an example in which the transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704 have the same structure, one embodiment of the present invention is not limited thereto. For example, the pixel portion 702 and the source driver circuit portion 704 may include different transistors. Specifically, a structure in which a staggered transistor is used in the pixel portion 702 and the inverted staggered transistor described in Embodiment 1 is used in the source driver circuit portion 704, or a structure in which the inverted staggered transistor described in Embodiment 1 is used in the pixel portion 702 and a staggered transistor is used in the source driver circuit portion 704 may be employed. Note that the term “source driver circuit portion 704” can be replaced by the term “gate driver circuit portion”.

The signal line 710 is formed through the same process as the conductive films functioning as source electrodes and drain electrodes of the transistors 750 and 752. In the case where the signal line 710 is formed using a material including a copper element, signal delay or the like due to wiring resistance is reduced, which enables display on a large screen.

The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and the FPC 716. Note that the connection electrode 760 is formed through the same process as the conductive films functioning as source electrodes and drain electrodes of the transistors 750 and 752. The connection electrode 760 is electrically connected to a terminal included in the FPC 716 through the anisotropic conductive film 780.

For example, glass substrates can be used as the first substrate 701 and the second substrate 705. As the first substrate 701 and the second substrate 705, flexible substrates may also be used. An example of the flexible substrate is a plastic substrate.

A structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selective etching of an insulating film and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Alternatively, a spherical spacer may also be used as the structure 778.

A light-blocking film 738 functioning as a black matrix, a coloring film 736 functioning as a color filter, and an insulating film 734 in contact with the light-blocking film 738 and the coloring film 736 are provided on the second substrate 705 side.

<3-2. Structure Example of Display Device Including Liquid Crystal Element>

The display device 700 in FIG. 22 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. The display device 700 in FIG. 22 can display an image in such a manner that transmission or non-transmission of light is controlled by the alignment state in the liquid crystal layer 776 that is changed depending on the voltage applied between the conductive film 772 and the conductive film 774.

The conductive film 772 is electrically connected to the conductive film functioning as the source electrode or the drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of the display element. The conductive film 772 functions as a reflective electrode. The display device 700 in FIG. 22 is what is called a reflective color liquid crystal display device that displays an image by utilizing external light that is reflected by the conductive film 772 and then extracted through the coloring film 736.

A conductive film that transmits visible light or a conductive film that reflects visible light can be used as the conductive film 772. For example, a material containing an element selected from indium (In), zinc (Zn), and tin (Sn) may be used for the conductive film that transmits visible light. For example, a material containing aluminum or silver may be used for the conductive film that reflects visible light. In this embodiment, a conductive film that reflects visible light is used as the conductive film 772.

Although FIG. 22 illustrates an example in which the conductive film 772 is connected to the conductive film functioning as the drain electrode of the transistor 750, one embodiment of the present invention is not limited to this example. For example, as illustrated in FIG. 23, the conductive film 772 may be electrically connected to the conductive film functioning as the drain electrode of the transistor 750 through a conductive film 777 functioning as a connection electrode. Note that the conductive film 777 is formed by a step of processing the conductive film to be the conductive film functioning as a second gate electrode of the transistor 750 and thus can be formed without adding a manufacturing step.

Note that the display device 700 in FIG. 22 is a reflective color liquid crystal display device given as an example, but a display type is not limited thereto. For example, a transmissive color liquid crystal display device in which the conductive film 772 is a conductive film that transmits visible light may be used. Alternatively, the display device 700 may be what is called a transflective color liquid crystal display device in which a reflective color liquid crystal display device and a transmissive color liquid crystal display device are combined.

FIG. 25 illustrates an example of a transmissive color liquid crystal display device. FIG. 25 is a cross-sectional view of a structure in which a liquid crystal element is used as the display element, taken along dashed-dotted line Q-R in FIG. 21. The display device 700 illustrated in FIG. 25 is an example of employing a horizontal electric field mode (e.g., an FFS mode) as a driving mode of the liquid crystal element. In the structure illustrated in FIG. 25, an insulating film 773 is provided over the conductive film 772 functioning as a pixel electrode, and the conductive film 774 is provided over the insulating film 773. In such a structure, the conductive film 774 functions as a common electrode, and an electric field generated between the conductive film 772 and the conductive film 774 through the insulating film 773 can control the alignment state in the liquid crystal layer 776.

Although not illustrated in FIG. 22 and FIG. 25, the conductive film 772 and/or the conductive film 774 may be provided with an alignment film on a side in contact with the liquid crystal layer 776. Although not illustrated in FIG. 22 and FIG. 25, an optical member (optical substrate) or the like, such as a polarizing member, a retardation member, or an anti-reflection member, may be provided as appropriate. For example, circular polarization may be obtained by using a polarizing substrate and a retardation substrate. In addition, a backlight, a sidelight, or the like may be used as a light source.

In the case where a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on conditions.

In the case where a horizontal electric field mode is employed, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase when the temperature of a cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which several weight percent or more of a chiral material is mixed is used for the liquid crystal layer in order to improve the temperature range. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral material has a short response time and optical isotropy, which eliminates the need for an alignment process. An alignment film does not need to be provided, and thus, rubbing treatment is not necessary; accordingly, electrostatic discharge damage caused by the rubbing treatment can be prevented, and defects and damage of a liquid crystal display device in the manufacturing process can be reduced. Moreover, the liquid crystal material that exhibits a blue phase has small viewing angle dependence.

In the case where a liquid crystal element is used as a display element, a twisted nematic (TN) mode, an in-plane switching (IPS) mode, a fringe field switching (FFS) mode, an axially symmetric aligned micro-cell (ASM) mode, an optical compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an anti-ferroelectric liquid crystal (AFLC) mode, or the like can be used.

Furthermore, a normally black liquid crystal display device such as a vertical alignment (VA) mode transmissive liquid crystal display device may also be used. There are some examples of a vertical alignment mode; for example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, and an ASV mode, or the like can be employed.

<3-3. Display Device Including Light-Emitting Element>

The display device 700 illustrated in FIG. 24 includes a light-emitting element 782. The light-emitting element 782 includes the conductive film 772, an EL layer 786, and a conductive film 788. The display device 700 illustrated in FIG. 24 can display an image by utilizing light emission from the EL layer 786 of the light-emitting element 782. Note that the EL layer 786 contains an organic compound or an inorganic compound such as a quantum dot.

Examples of materials that can be used for an organic compound include a fluorescent material and a phosphorescent material. Examples of materials that can be used for a quantum dot include a colloidal quantum dot material, an alloyed quantum dot material, a core-shell quantum dot material, and a core quantum dot material. A material containing elements belonging to Groups 12 and 16, elements belonging to Groups 13 and 15, or elements belonging to Groups 14 and 16, may be used. Alternatively, a quantum dot material containing an element such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), or aluminum (Al) may be used.

In the display device 700 in FIG. 24, an insulating film 730 is provided over the planarization insulating film 770 and the conductive film 772. The insulating film 730 covers part of the conductive film 772. Note that the light-emitting element 782 has a top-emission structure. Thus, the conductive film 788 has a light-transmitting property and transmits light emitted from the EL layer 786. Although the top-emission structure is described as an example in this embodiment, the structure is not limited thereto. For example, a bottom-emission structure in which light is emitted to the conductive film 772 side or a dual-emission structure in which light is emitted to both the conductive film 772 side and the conductive film 788 side may also be employed.

The coloring film 736 is provided to overlap with the light-emitting element 782, and the light-blocking film 738 is provided in the lead wiring portion 711 and the source driver circuit portion 704 to overlap with the insulating film 730. The coloring film 736 and the light-blocking film 738 are covered with the insulating film 734. A space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. The structure of the display device 700 is not limited to the example in FIG. 24, in which the coloring film 736 is provided. For example, a structure without the coloring film 736 may also be employed in the case where the EL layer 786 is formed by separate coloring.

<3-4. Structure Example of Display Device Provided with Input/Output Device>

An input/output device may be provided in the display device 700 illustrated in FIG. 24 and FIG. 25. As an example of the input/output device, a touch panel or the like can be given.

FIG. 26 and FIG. 27 illustrate structures in which the display device 700 in FIG. 24 and FIG. 25 includes a touch panel 791.

FIG. 26 is a cross-sectional view of the structure in which the touch panel 791 is provided in the display device 700 illustrated in FIG. 24, and FIG. 27 is a cross-sectional view of the structure in which the touch panel 791 is provided in the display device 700 illustrated in FIG. 25.

First, the touch panel 791 illustrated in FIG. 26 and FIG. 27 is described below.

The touch panel 791 illustrated in FIG. 26 and FIG. 27 is what is called an in-cell touch panel provided between the substrate 705 and the coloring film 736. The touch panel 791 is formed on the substrate 705 side before the light-blocking film 738 and the coloring film 736 is formed.

Note that the touch panel 791 includes the light-blocking film 738, an insulating film 792, an electrode 793, an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. Changes in the mutual capacitance in the electrodes 793 and 794 can be detected when an object such as a finger or a stylus approaches, for example.

A portion in which the electrode 793 intersects with the electrode 794 is illustrated in the upper portion of the transistor 750 illustrated in FIG. 26 and FIG. 27. The electrode 796 is electrically connected to the two electrodes 793 between which the electrode 794 is sandwiched through openings provided in the insulating film 795. Note that a structure in which a region where the electrode 796 is provided is provided in the pixel portion 702 is illustrated in FIG. 26 and FIG. 27 as an example; however, one embodiment of the present invention is not limited thereto. For example, the region where the electrode 796 is provided may be provided in the source driver circuit portion 704.

The electrode 793 and the electrode 794 are provided in a region overlapping with the light-blocking film 738. As illustrated in FIG. 26, it is preferable that the electrode 793 do not overlap with the light-emitting element 782. As illustrated in FIG. 27, it is preferable that the electrode 793 do not overlap with the liquid crystal element 775. In other words, the electrode 793 has an opening in a region overlapping with the light-emitting element 782 and the liquid crystal element 775. That is, the electrode 793 has a mesh shape. With such a structure, the electrode 793 does not block light emitted from the light-emitting element 782, or alternatively the electrode 793 does not block light transmitted through the liquid crystal element 775. Thus, since luminance is hardly reduced even when the touch panel 791 is provided, a display device with high visibility and low power consumption can be obtained. Note that the electrode 794 can have a structure similar to that of the electrode 793.

Since the electrode 793 and the electrode 794 do not overlap with the light-emitting element 782, a metal material having low transmittance with respect to visible light can be used for the electrode 793 and the electrode 794. Since the electrode 793 and the electrode 794 do not overlap with the liquid crystal element 775, a metal material having low transmittance with respect to visible light can be used for the electrode 793 and the electrode 794.

Thus, as compared with the case of using an oxide material whose transmittance of visible light is high, resistance of the electrodes 793 and 794 can be reduced, whereby sensitivity of the sensor of the touch panel can be increased.

For example, a conductive nanowire may be used for the electrodes 793, 794, and 796. The nanowire may have a mean diameter of greater than or equal to 1 nm and less than or equal to 100 nm, preferably greater than or equal to 5 nm and less than or equal to 50 nm, further preferably greater than or equal to 5 nm and less than or equal to 25 nm. As the nanowire, a carbon nanotube or a metal nanowire such as an Ag nanowire, a Cu nanowire, or an Al nanowire may be used. For example, in the case where an Ag nanowire is used for any one of or all of electrodes 664, 665, and 667, the transmittance of visible light can be greater than or equal to 89% and the sheet resistance can be greater than or equal to 40 Ω/square and less than or equal to 100 Ω/square.

Although the structure of the in-cell touch panel is illustrated in FIG. 26 and FIG. 27, one embodiment of the present invention is not limited thereto. For example, a touch panel formed over the display device 700, what is called an on-cell touch panel, or a touch panel attached to the display device 700, what is called an out-cell touch panel may be used.

In this manner, the display device of one embodiment of the present invention can be combined with various types of touch panels.

The structures described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

Embodiment 4

In this embodiment, a display device including a semiconductor device of one embodiment of the present invention is described with reference to FIGS. 28A to 28C.

<4. Circuit Configuration of Display Device>

A display device illustrated in FIG. 28A includes a region including pixels of display elements (hereinafter referred to as a pixel portion 502), a circuit portion that is provided outside the pixel portion 502 and includes a circuit for driving the pixels (hereinafter, the circuit portion is referred to as a driver circuit portion 504), circuits having a function of protecting elements (hereinafter, the circuits are referred to as protection circuits 506), and a terminal portion 507. Note that the protection circuits 506 are not necessarily provided.

Part or the whole of the driver circuit portion 504 is preferably formed over a substrate over which the pixel portion 502 is formed. Thus, the number of components and the number of terminals can be reduced. When part or the whole of the driver circuit portion 504 is not formed over the substrate over which the pixel portion 502 is formed, the part or the whole of the driver circuit portion 504 can be mounted by COG or tape automated bonding (TAB).

The pixel portion 502 includes a plurality of circuits for driving display elements arranged in X (X is a natural number of 2 or more) rows and Y (Y is a natural number of 2 or more) columns (hereinafter, the circuits are referred to as pixel circuits 501). The driver circuit portion 504 includes driver circuits such as a circuit for supplying a signal (scan signal) to select a pixel (hereinafter, the circuit is referred to as a gate driver 504 a) and a circuit for supplying a signal (data signal) to drive a display element in a pixel (hereinafter, the circuit is referred to as a source driver 504 b).

The gate driver 504 a includes a shift register or the like. The gate driver 504 a receives a signal for driving the shift register through the terminal portion 507 and outputs a signal. For example, the gate driver 504 a receives a start pulse signal, a clock signal, or the like and outputs a pulse signal. The gate driver 504 a has a function of controlling the potentials of wirings supplied with scan signals (hereinafter referred to as scan lines GL_1 to GL_X). Note that a plurality of gate drivers 504 a may be provided to control the scan lines GL_1 to GL_X separately. Alternatively, the gate driver 504 a has a function of supplying an initialization signal. Without being limited thereto, another signal can be supplied from the gate driver 504 a.

The source driver 504 b includes a shift register or the like. The source driver 504 b receives a signal (image signal) from which a data signal is generated, as well as a signal for driving the shift register, through the terminal portion 507. The source driver 504 b has a function of generating a data signal to be written to the pixel circuit 501 from the image signal. In addition, the source driver 504 b has a function of controlling output of a data signal in response to a pulse signal produced by input of a start pulse signal, a clock signal, or the like. Furthermore, the source driver 504 b has a function of controlling the potentials of wirings supplied with data signals (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504 b has a function of supplying an initialization signal. Without being limited thereto, another signal can be supplied from the source driver 504 b.

The source driver 504 b includes a plurality of analog switches, for example. The source driver 504 b can output, as data signals, time-divided image signals obtained by sequentially turning on the plurality of analog switches. The source driver 504 b may include a shift register or the like.

A pulse signal and a data signal are input to each of the plurality of pixel circuits 501 through one of the plurality of scan lines GL supplied with scan signals and one of the plurality of data lines DL supplied with data signals, respectively. Writing and holding of the data signal in each of the plurality of pixel circuits 501 are controlled by the gate driver 504 a. For example, to the pixel circuit 501 in the m-th row and the n-th column (m is a natural number of X or less, and n is a natural number of Y or less), a pulse signal is input from the gate driver 504 a through the scan line GL_m, and a data signal is input from the source driver 504 b through the data line DL_n in accordance with the potential of the scan line GL_m.

The protection circuit 506 in FIG. 28A is connected to, for example, the scan line GL between the gate driver 504 a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to the data line DL between the source driver 504 b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to a wiring between the gate driver 504 a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to a wiring between the source driver 504 b and the terminal portion 507. Note that the terminal portion 507 refers to a portion having terminals for inputting power, control signals, and image signals from external circuits to the display device.

The protection circuit 506 electrically connects a wiring connected to the protection circuit to another wiring when a potential out of a certain range is supplied to the wiring connected to the protection circuit.

As illustrated in FIG. 28A, the protection circuits 506 provided for the pixel portion 502 and the driver circuit portion 504 can improve the resistance of the display device to overcurrent generated by electrostatic discharge (ESD) or the like. Note that the configuration of the protection circuits 506 is not limited thereto; for example, the protection circuit 506 can be connected to the gate driver 504 a or the source driver 504 b. Alternatively, the protection circuit 506 can be connected to the terminal portion 507.

One embodiment of the present invention is not limited to the example in FIG. 28A, in which the driver circuit portion 504 includes the gate driver 504 a and the source driver 504 b. For example, only the gate driver 504 a may be formed, and a separately prepared substrate over which a source driver circuit is formed (e.g., a driver circuit board formed using a single-crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

Each of the plurality of pixel circuits 501 in FIG. 28A can have the configuration illustrated in FIG. 28B, for example.

The pixel circuit 501 in FIG. 28B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. As the transistor 550, the transistor described in the above embodiment can be used.

The potential of one of a pair of electrodes of the liquid crystal element 570 is set as appropriate in accordance with the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 depends on data written thereto. A common potential may be supplied to the one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. The potential supplied to the one of the pair of electrodes of the liquid crystal element 570 in the pixel circuit 501 may differ between rows.

Examples of a method for driving the display device including the liquid crystal element 570 include a TN mode, an STN mode, a VA mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an anti-ferroelectric liquid crystal (AFLC) mode, an MVA mode, a patterned vertical alignment (PVA) mode, an IPS mode, an FFS mode, and a transverse bend alignment (TBA) mode. Other examples of the method for driving the display device include an electrically controlled birefringence (ECB) mode, a polymer-dispersed liquid crystal (PDLC) mode, a polymer network liquid crystal (PNLC) mode, and a guest-host mode. Without being limited thereto, various liquid crystal elements and driving methods can be used.

In the pixel circuit 501 in the m-th row and the n-th column, one of a source electrode and a drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other of the source electrode and the drain electrode of the transistor 550 is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. A gate electrode of the transistor 550 is electrically connected to the scan line GL_m. The transistor 550 is configured to be turned on or off to control whether a data signal is written.

One of a pair of electrodes of the capacitor 560 is electrically connected to a wiring through which a potential is supplied (hereinafter referred to as a potential supply line VL), and the other of the pair of electrodes of the capacitor 560 is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The potential of the potential supply line VL is set as appropriate in accordance with the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

For example, in the display device including the pixel circuits 501 in FIG. 28B, the gate driver 504 a in FIG. 28A sequentially selects the pixel circuits 501 row by row to turn on the transistors 550, and data signals are written.

When the transistor 550 is turned off, the pixel circuit 501 to which the data has been written is brought into a holding state. This operation is sequentially performed row by row; thus, an image can be displayed.

Alternatively, each of the plurality of pixel circuits 501 in FIG. 28A can have the configuration illustrated in FIG. 28C, for example.

The pixel circuit 501 in FIG. 28C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The transistor described in the above embodiment can be used as the transistor 552 and/or the transistor 554.

One of a source electrode and a drain electrode of the transistor 552 is electrically connected to a wiring through which a data signal is supplied (hereinafter referred to as a data line DL_n). A gate electrode of the transistor 552 is electrically connected to a wiring through which a gate signal is supplied (hereinafter referred to as a scan line GL_m).

The transistor 552 is configured to be turned on or off to control whether a data signal is written.

One of a pair of electrodes of the capacitor 562 is electrically connected to a wiring through which a potential is supplied (hereinafter referred to as a potential supply line VL_a), and the other of the pair of electrodes of the capacitor 562 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

The capacitor 562 functions as a storage capacitor for storing written data.

One of a source electrode and a drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. A gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

One of an anode and a cathode of the light-emitting element 572 is electrically connected to a potential supply line VL_b, and the other of the anode and the cathode of the light-emitting element 572 is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

As the light-emitting element 572, an organic electroluminescent element (also referred to as an organic EL element) can be used, for example. Note that the light-emitting element 572 is not limited thereto and may be an inorganic EL element including an inorganic material.

A high power supply potential VDD is supplied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is supplied to the other of the potential supply line VL_a and the potential supply line VL_b.

In the display device including the pixel circuits 501 in FIG. 28C, the gate driver 504 a in FIG. 28A sequentially selects the pixel circuits 501 row by row to turn on the transistors 552, and data signals are written.

When the transistor 552 is turned off, the pixel circuit 501 to which the data has been written is brought into a holding state. Furthermore, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled in accordance with the potential of the written data signal. The light-emitting element 572 emits light with a luminance corresponding to the amount of flowing current. This operation is sequentially performed row by row; thus, an image can be displayed.

The structures described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

Embodiment 5

In this embodiment, circuit configuration examples to which the transistors described in the above embodiments can be applied are described with reference to FIGS. 29A to 29C, FIGS. 30A to 30C, FIGS. 31A and 31B, and FIGS. 32A and 32B.

Note that in the following description in this embodiment, the transistor including an oxide semiconductor described in the above embodiment is referred to as an OS transistor.

<5. Configuration Example of Inverter Circuit>

FIG. 29A is a circuit diagram of an inverter that can be used for a shift register, a buffer, or the like included in the driver circuit. An inverter 800 outputs a signal whose logic is inverted from the logic of a signal supplied to an input terminal IN to an output terminal OUT. The inverter 800 includes a plurality of OS transistors. A signal S_(BG) can switch electrical characteristics of the OS transistors.

FIG. 29B illustrates an example of the inverter 800. The inverter 800 includes an OS transistor 810 and an OS transistor 820. The inverter 800 can be formed using only n-channel transistors; thus, the inverter 800 can be formed at lower cost than an inverter formed using a complementary metal oxide semiconductor (i.e., a CMOS inverter).

Note that the inverter 800 including the OS transistors can be provided over a CMOS circuit including Si transistors. Since the inverter 800 can be provided so as to overlap with the CMOS circuit, no additional area is required for the inverter 800, and thus, an increase in the circuit area can be suppressed.

Each of the OS transistors 810 and 820 includes a first gate functioning as a front gate, a second gate functioning as a back gate, a first terminal functioning as one of a source and a drain, and a second terminal functioning as the other of the source and the drain.

The first gate of the OS transistor 810 is connected to its second terminal. The second gate of the OS transistor 810 is connected to a wiring that supplies the signal S_(BG). The first terminal of the OS transistor 810 is connected to a wiring that supplies a voltage VDD. The second terminal of the OS transistor 810 is connected to the output terminal OUT.

The first gate of the OS transistor 820 is connected to the input terminal IN. The second gate of the OS transistor 820 is connected to the input terminal IN. The first terminal of the OS transistor 820 is connected to the output terminal OUT. The second terminal of the OS transistor 820 is connected to a wiring that supplies a voltage VSS.

FIG. 29C is a timing chart illustrating the operation of the inverter 800. The timing chart in FIG. 29C illustrates changes of a signal waveform of the input terminal IN, a signal waveform of the output terminal OUT, a signal waveform of the signal S_(BG), and the threshold voltage of the OS transistor 810.

The signal S_(BG) can be supplied to the second gate of the OS transistor 810 to control the threshold voltage of the OS transistor 810.

The signal S_(BG) includes a voltage V_(BG) _(_) _(A) for shifting the threshold voltage in the negative direction and a voltage V_(BG) _(_) _(B) for shifting the threshold voltage in the positive direction. The threshold voltage of the OS transistor 810 can be shifted in the negative direction to be a threshold voltage V_(TH) _(_) _(A) when the voltage V_(BG) _(_) _(A) is applied to the second gate. The threshold voltage of the OS transistor 810 can be shifted in the positive direction to be a threshold voltage V_(TH) _(_) _(B) when the voltage V_(BG) _(_) _(B) is applied to the second gate.

To visualize the above description, FIG. 30A shows an I_(d)-V_(g) curve, which is one of the electrical characteristics of a transistor.

When a high voltage such as the voltage V_(BG) _(_) _(A) is applied to the second gate, the electrical characteristics of the OS transistor 810 can be shifted to match a curve shown by a dashed line 840 in FIG. 30A. When a low voltage such as the voltage V_(BG) _(_) _(B) is applied to the second gate, the electrical characteristics of the OS transistor 810 can be shifted to match a curve shown by a solid line 841 in FIG. 30A. As shown in FIG. 30A, switching the signal S_(BG) between the voltage V_(BG) _(_) _(A) and the voltage V_(BG) _(_) _(B) enables the threshold voltage of the OS transistor 810 to be shifted in the positive direction or the negative direction.

The shift of the threshold voltage in the positive direction toward the threshold voltage V_(TH) _(_) _(B) can make current less likely to flow in the OS transistor 810. FIG. 30B visualizes the state.

As illustrated in FIG. 30B, a current I_(B) that flows in the OS transistor 810 can be extremely low. Thus, when a signal supplied to the input terminal IN is at a high level and the OS transistor 820 is on (ON), the voltage of the output terminal OUT can drop sharply.

Since a state in which current is less likely to flow in the OS transistor 810 as illustrated in FIG. 30B can be obtained, a signal waveform 831 of the output terminal in the timing chart in FIG. 29C can be made steep. Shoot-through current between the wiring that supplies the voltage VDD and the wiring that supplies the voltage VSS can be low, leading to low-power operation.

The shift of the threshold voltage in the negative direction toward the threshold voltage V_(TH) _(_) _(A) can make current flow easily in the OS transistor 810. FIG. 30C visualizes the state. As illustrated in FIG. 30C, a current I_(A) flowing at this time can be higher than at least the current h. Thus, when a signal supplied to the input terminal IN is at a low level and the OS transistor 820 is off (OFF), the voltage of the output terminal OUT can be increased sharply. Since a state in which current is likely to flow in the OS transistor 810 as illustrated in FIG. 30C can be obtained, a signal waveform 832 of the output terminal in the timing chart in FIG. 29C can be made steep.

Note that the threshold voltage of the OS transistor 810 is preferably controlled by the signal S_(BG) before the state of the OS transistor 820 is switched, i.e., before time T1 or time T2. For example, as in FIG. 29C, it is preferable that the threshold voltage of the OS transistor 810 be switched from the threshold voltage V_(TH) _(_) _(A) to the threshold voltage V_(TH) _(_) _(B) before time T1 at which the level of the signal supplied to the input terminal IN is switched to a high level. Moreover, as in FIG. 29C, it is preferable that the threshold voltage of the OS transistor 810 be switched from the threshold voltage V_(TH) _(_) _(B) to the threshold voltage V_(TH) _(_) _(A) before time T2 at which the level of the signal supplied to the input terminal IN is switched to a low level.

Although the timing chart in FIG. 29C illustrates the structure in which the level of the signal S_(BG) is switched in accordance with the signal supplied to the input terminal IN, a different structure may be employed in which voltage for controlling the threshold voltage is held by the second gate of the OS transistor 810 in a floating state, for example. FIG. 31A illustrates an example of such a circuit configuration.

The circuit configuration in FIG. 31A is the same as that in FIG. 29B, except that an OS transistor 850 is added. A first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810. A second terminal of the OS transistor 850 is connected to a wiring that supplies the voltage V_(BG) _(_) _(B) (or the voltage V_(BG) _(_) _(A)). A first gate of the OS transistor 850 is connected to a wiring that supplies a signal SF. A second gate of the OS transistor 850 is connected to the wiring that supplies the voltage V_(BG) _(_) _(B) (or the voltage V_(BG) _(_) _(A)).

The operation with the circuit configuration in FIG. 31A is described with reference to a timing chart in FIG. 31B.

The voltage for controlling the threshold voltage of the OS transistor 810 is supplied to the second gate of the OS transistor 810 before time T3 at which the level of the signal supplied to the input terminal IN is switched to a high level. The signal SF is set to a high level and the OS transistor 850 is turned on, so that the voltage V_(BG) _(_) _(B) for controlling the threshold voltage is supplied to a node N_(BG).

The OS transistor 850 is turned off after the voltage of the node N_(BG) becomes V_(BG) _(_) _(B). Since the off-state current of the OS transistor 850 is extremely low, the voltage V_(BG) _(_) _(B) held by the node N_(BG) can be retained while the OS transistor 850 remains off. Thus, the number of times the voltage V_(BG) _(_) _(B) is supplied to the second gate of the OS transistor 850 can be reduced and accordingly, the power consumption for rewriting the voltage V_(BG) _(_) _(B) can be reduced.

Although FIG. 29B and FIG. 31A each illustrate the case where the voltage is supplied to the second gate of the OS transistor 810 by control from the outside, a different structure may be employed in which voltage for controlling the threshold voltage is generated on the basis of the signal supplied to the input terminal IN and supplied to the second gate of the OS transistor 810, for example. FIG. 32A illustrates an example of such a circuit configuration.

The circuit configuration in FIG. 32A is the same as that in FIG. 29B, except that a CMOS inverter 860 is provided between the input terminal IN and the second gate of the OS transistor 810. An input terminal of the CMOS inverter 860 is connected to the input terminal IN. An output terminal of the CMOS inverter 860 is connected to the second gate of the OS transistor 810.

The operation with the circuit configuration in FIG. 32A is described with reference to a timing chart in FIG. 32B. The timing chart in FIG. 32B illustrates changes of a signal waveform of the input terminal IN, a signal waveform of the output terminal OUT, an output waveform IN_B of the CMOS inverter 860, and a threshold voltage of the OS transistor 810.

The output waveform IN_B that corresponds to a signal whose logic is inverted from the logic of the signal supplied to the input terminal IN can be used as a signal that controls the threshold voltage of the OS transistor 810. Thus, the threshold voltage of the OS transistor 810 can be controlled as described with reference to FIGS. 30A to 30C. For example, the signal supplied to the input terminal IN is at a high level and the OS transistor 820 is turned on at time T4 in FIG. 32B. At this time, the output waveform IN_B is at a low level. Accordingly, current can be made less likely to flow in the OS transistor 810; thus, the voltage of the output terminal OUT can be sharply decreased.

Moreover, the signal supplied to the input terminal IN is at a low level and the OS transistor 820 is turned off at time T5 in FIG. 32B. At this time, the output waveform IN_B is at a high level. Accordingly, current can easily flow in the OS transistor 810; thus, a rise in the voltage of the output terminal OUT can be made steep.

As described above, in the configuration of the inverter including the OS transistor in this embodiment, the voltage of the back gate is switched in accordance with the logic of the signal supplied to the input terminal IN. In such a configuration, the threshold voltage of the OS transistor can be controlled. The control of the threshold voltage of the OS transistor by the signal supplied to the input terminal IN can cause a steep change in the voltage of the output terminal OUT. Moreover, shoot-through current between the wirings that supply power supply voltages can be reduced. Thus, power consumption can be reduced.

The structures described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

Embodiment 6

In this embodiment, examples of a semiconductor device in which the transistor including an oxide semiconductor (OS transistor) described in any of the above embodiments is used in a plurality of circuits are described with reference to FIGS. 33A to 33E, FIGS. 34A and 34B, FIGS. 35A and 35B, and FIGS. 36A to 36C.

<6. Circuit Configuration Example of Semiconductor Device>

FIG. 33A is a block diagram of a semiconductor device 900. The semiconductor device 900 includes a power supply circuit 901, a circuit 902, a voltage generation circuit 903, a circuit 904, a voltage generation circuit 905, and a circuit 906.

The power supply circuit 901 is a circuit that generates a voltage V_(ORG) used as a reference. The voltage V_(ORG) is not necessarily one voltage and can be a plurality of voltages. The voltage V_(ORG) can be generated on the basis of a voltage V₀ supplied from the outside of the semiconductor device 900. The semiconductor device 900 can generate the voltage V_(ORG) on the basis of one power supply voltage supplied from the outside. Thus, the semiconductor device 900 can operate without supply of a plurality of power supply voltages from the outside.

The circuits 902, 904, and 906 operate with different power supply voltages. For example, the power supply voltage of the circuit 902 is a voltage based on the voltage V_(ORG) and the voltage V_(SS) (V_(ORG)>V_(SS)), the power supply voltage of the circuit 904 is a voltage based on a voltage V_(POG) and the voltage V_(SS)(V_(POG)>V_(ORG)), and the power supply voltages of the circuit 906 are voltages based on the voltage V_(ORG), the voltage V_(SS), and a voltage V_(NEG) (V_(ORG)>V_(SS)>V_(NEG)). When the voltage V_(SS) is equal to a ground potential (GND), the kinds of voltages generated by the power supply circuit 901 can be reduced.

The voltage generation circuit 903 is a circuit that generates the voltage V_(POG). The voltage generation circuit 903 can generate the voltage V_(POG) on the basis of the voltage V_(ORG) supplied from the power supply circuit 901. Thus, the semiconductor device 900 including the circuit 904 can operate on the basis of one power supply voltage supplied from the outside.

The voltage generation circuit 905 is a circuit that generates the voltage V_(NEG). The voltage generation circuit 905 can generate the voltage V_(NEG) on the basis of the voltage V_(ORG) supplied from the power supply circuit 901. Thus, the semiconductor device 900 including the circuit 906 can operate on the basis of one power supply voltage supplied from the outside.

FIG. 33B illustrates an example of the circuit 904 that operates with the voltage V_(POG) and FIG. 33C illustrates an example of a waveform of a signal for operating the circuit 904.

FIG. 33B illustrates a transistor 911. A signal supplied to a gate of the transistor 911 is generated on the basis of, for example, the voltage V_(POG) and the voltage V_(SS). The signal is generated on the basis of the voltage V_(POG) to turn on the transistor 911 and on the basis of the voltage V_(SS) to turn off the transistor 911. As illustrated in FIG. 33C, the voltage V_(POG) is higher than the voltage V_(ORG). Thus, a source (S) and a drain (D) of the transistor 911 can be electrically connected to each other without fail. As a result, the frequency of malfunction of the circuit 904 can be reduced.

FIG. 33D illustrates an example of the circuit 906 that operates with the voltage V_(NEG) and FIG. 33E illustrates an example of a waveform of a signal for operating the circuit 906.

FIG. 33D illustrates a transistor 912 having a back gate. A signal supplied to a gate of the transistor 912 is generated on the basis of, for example, the voltage V_(ORG) and the voltage V_(SS). The signal is generated on the basis of the voltage V_(ORG) to turn on the transistor 912 and on the basis of the voltage V_(SS) to turn off the transistor 912. A signal supplied to the back gate of the transistor 912 is generated on the basis of the voltage V_(NEG). As illustrated in FIG. 33E, the voltage V_(NEG) is lower than the voltage V_(SS)(GND). Thus, the threshold voltage of the transistor 912 can be controlled to shift in the positive direction. Thus, the transistor 912 can be turned off without fail and a current flowing between a source (S) and a drain (D) can be reduced. As a result, the frequency of malfunction of the circuit 906 can be reduced and power consumption thereof can be reduced.

The voltage V_(NEG) may be directly supplied to the back gate of the transistor 912. Alternatively, a signal supplied to the gate of the transistor 912 may be generated on the basis of the voltage V_(ORG) and the voltage V_(NEG) and the generated signal may also be supplied to the back gate of the transistor 912.

FIGS. 34A and 34B illustrate a modification example of FIGS. 33D and 33E.

In a circuit diagram illustrated in FIG. 34A, a transistor 922 whose on/off state can be controlled by a control circuit 921 is provided between the voltage generation circuit 905 and the circuit 906. The transistor 922 is an n-channel OS transistor. The control signal S_(BG) output from the control circuit 921 is a signal for controlling the on/off state of the transistor 922. Transistors 912A and 912B included in the circuit 906 are OS transistors like the transistor 922.

A timing chart in FIG. 34B shows changes in a potential of the control signal S_(BG) and a potential of a node N_(BG). The potential of the node N_(BG) indicates the states of potentials of back gates of the transistors 912A and 912B. When the control signal S_(BG) is at a high level, the transistor 922 is turned on and the voltage of the node N_(BG) becomes the voltage V_(NEG). Then, when the control signal S_(BG) is at a low level, the node N_(BG) is brought into an electrically floating state. Since the transistor 922 is an OS transistor, its off-state current is small. Accordingly, even when the node N_(BG) is in an electrically floating state, the voltage V_(NEG) that has been supplied can be held.

FIG. 35A illustrates an example of a circuit configuration applicable to the above-described voltage generation circuit 903. The voltage generation circuit 903 illustrated in FIG. 35A is a five-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV. A clock signal CLK is supplied to the capacitors C1 to C5 directly or through the inverter INV. When a power supply voltage of the inverter INV is a voltage applied on the basis of the voltage V_(ORG) and the voltage V_(SS), the voltage V_(POG), which has been increased to a positive voltage having a positively quintupled value of the voltage V_(ORG) by application of the clock signal CLK, can be obtained. Note that the forward voltage of the diodes D1 to D5 is 0 V. The number of stages of the charge pump can be changed to obtain a desired voltage V_(POG).

FIG. 35B illustrates an example of a circuit configuration applicable to the above-described voltage generation circuit 905. The voltage generation circuit 905 illustrated in FIG. 35B is a four-stage charge pump including the diodes D1 to D5, the capacitors C1 to C5, and the inverter INV. The clock signal CLK is supplied to the capacitors C1 to C5 directly or through the inverter INV. When a power supply voltage of the inverter INV is a voltage applied on the basis of the voltage V_(ORG) and the voltage V_(SS), the voltage V_(NEG), which has been reduced from GND (i.e., the voltage V_(SS)) to a negative voltage having a negatively quadrupled value of the voltage V_(ORG) by application of the clock signal CLK, can be obtained. Note that the forward voltage of the diodes D1 to D5 is 0 V. The number of stages of the charge pump can be changed to obtain a desired voltage V_(NEG).

The circuit configuration of the voltage generation circuit 903 is not limited to the configuration in the circuit diagram illustrated in FIG. 35A. Modification examples of the voltage generation circuit 903 are illustrated in FIGS. 36A to 36C. Note that further modification examples of the voltage generation circuit 903 can be realized by changing voltages supplied to wirings or arrangement of elements in voltage generation circuits 903A to 903C illustrated in FIGS. 36A to 36C.

The voltage generation circuit 903A illustrated in FIG. 36A includes transistors M1 to M10, capacitors C11 to C14, and an inverter INV₁. The clock signal CLK is supplied to gates of the transistors M1 to M10 directly or through the inverter INV₁. By application of the clock signal CLK, the voltage V_(POG), which has been increased to a positive voltage having a positively quadrupled value of the voltage V_(ORG), can be obtained. The number of stages can be changed to obtain a desired voltage V_(POG). In the voltage generation circuit 903A in FIG. 36A, off-state current of each of the transistors M1 to M10 can be small when the transistors M1 to M10 are OS transistors, and leakage of charge held in the capacitors C11 to C14 can be suppressed. Accordingly, the voltage V_(ORG) can be efficiently increased to the voltage V_(POG).

The voltage generation circuit 903B illustrated in FIG. 36B includes transistors M11 to M14, capacitors C15 and C16, and an inverter INV₂. The clock signal CLK is supplied to gates of the transistors M11 to M14 directly or through the inverter INV₂. By application of the clock signal CLK, the voltage V_(POG), which has been increased to a positive voltage having a positively doubled value of the voltage V_(ORG), can be obtained. In the voltage generation circuit 903B in FIG. 36B, off-state current of each of the transistors M11 to M14 can be small when the transistors M11 to M14 are OS transistors, and leakage of charge held in the capacitors C15 and C16 can be suppressed. Accordingly, the voltage V_(ORG) can be efficiently increased to the voltage V_(POG).

A voltage generation circuit 903C illustrated in FIG. 36C includes an inductor Ind1, a transistor M15, a diode D6, and a capacitor C17. The on/off state of the transistor M15 is controlled by a control signal EN. Owing to the control signal EN, the voltage V_(POG) increased from the voltage V_(ORG) can be obtained. Since the voltage generation circuit 903C in FIG. 36C increases the voltage using the inductor Ind1, the voltage can be efficiently increased.

As described above, in any of the structures of this embodiment, a voltage required for circuits included in a semiconductor device can be internally generated. Thus, in the semiconductor device, the number of power supply voltages supplied from the outside can be reduced.

The structures and the like described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

Embodiment 7

In this embodiment, a display module and electronic devices, each of which includes a semiconductor device of one embodiment of the present invention, are described with reference to FIG. 37, FIGS. 38A to 38E, FIGS. 39A to 39G, and FIGS. 40A and 40B.

<7-1. Display Module>

In a display module 7000 illustrated in FIG. 37, a touch panel 7004 connected to an FPC 7003, a display panel 7006 connected to an FPC 7005, a backlight 7007, a frame 7009, a printed board 7010, and a battery 7011 are provided between an upper cover 7001 and a lower cover 7002.

The semiconductor device of one embodiment of the present invention can be used for the display panel 7006, for example.

The shapes and sizes of the upper cover 7001 and the lower cover 7002 can be changed as appropriate in accordance with the sizes of the touch panel 7004 and the display panel 7006.

The touch panel 7004 can be a resistive touch panel or a capacitive touch panel and overlap with the display panel 7006. Alternatively, a counter substrate (sealing substrate) of the display panel 7006 can have a touch panel function. Alternatively, a photosensor may be provided in each pixel of the display panel 7006 to form an optical touch panel.

The backlight 7007 includes a light source 7008. One embodiment of the present invention is not limited to the structure in FIG. 37, in which the light source 7008 is provided over the backlight 7007. For example, a structure in which the light source 7008 is provided at an end portion of the backlight 7007 and a light diffusion plate is further provided may be employed. Note that the backlight 7007 need not be provided in the case where a self-luminous light-emitting element such as an organic EL element is used or in the case where a reflective panel or the like is employed.

The frame 7009 protects the display panel 7006 and functions as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board 7010. The frame 7009 may also function as a radiator plate.

The printed board 7010 includes a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power source for supplying power to the power supply circuit, an external commercial power source or the separate battery 7011 may be used. The battery 7011 can be omitted in the case where a commercial power source is used.

The display module 7000 may be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet.

<7-2. Electronic Device 1>

Next, FIGS. 38A to 38E illustrate examples of electronic devices.

FIG. 38A is an external view of a camera 8000 to which a finder 8100 is attached.

The camera 8000 includes a housing 8001, a display portion 8002, an operation button 8003, a shutter button 8004, and the like. Furthermore, an attachable lens 8006 is attached to the camera 8000.

Although the lens 8006 of the camera 8000 here is detachable from the housing 8001 for replacement, the lens 8006 may be included in the housing 8001.

Images can be taken with the camera 8000 at the press of the shutter button 8004. In addition, images can be taken at the touch of the display portion 8002 that serves as a touch panel.

The housing 8001 of the camera 8000 includes a mount including an electrode, so that the finder 8100, a stroboscope, or the like can be connected to the housing 8001.

The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

The housing 8101 includes a mount for engagement with the mount of the camera 8000 so that the finder 8100 can be connected to the camera 8000. The mount includes an electrode, and an image or the like received from the camera 8000 through the electrode can be displayed on the display portion 8102.

The button 8103 serves as a power button. The on/off state of the display portion 8102 can be turned on and off with the button 8103.

A display device of one embodiment of the present invention can be used in the display portion 8002 of the camera 8000 and the display portion 8102 of the finder 8100.

Although the camera 8000 and the finder 8100 are separate and detachable electronic devices in FIG. 38A, the housing 8001 of the camera 8000 may include a finder having a display device.

FIG. 38B is an external view of a head-mounted display 8200.

The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. The mounting portion 8201 includes a battery 8206.

Power is supplied from the battery 8206 to the main body 8203 through the cable 8205. The main body 8203 includes a wireless receiver or the like to receive video data, such as image data, and display it on the display portion 8204. The movement of the eyeball and the eyelid of a user is captured by a camera in the main body 8203 and then coordinates of the points the user looks at are calculated using the captured data to utilize the eye of the user as an input means.

The mounting portion 8201 may include a plurality of electrodes so as to be in contact with the user. The main body 8203 may be configured to sense current flowing through the electrodes with the movement of the user's eyeball to recognize the direction of his or her eyes. The main body 8203 may be configured to sense current flowing through the electrodes to monitor the user's pulse. The mounting portion 8201 may include sensors, such as a temperature sensor, a pressure sensor, or an acceleration sensor so that the user's biological information can be displayed on the display portion 8204. The main body 8203 may be configured to sense the movement of the user's head or the like to move an image displayed on the display portion 8204 in synchronization with the movement of the user's head or the like.

The display device of one embodiment of the present invention can be used in the display portion 8204.

FIGS. 38C to 38E are external views of a head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display portion 8302, an object for fixing, such as a band, 8304, and a pair of lenses 8305.

A user can see display on the display portion 8302 through the lenses 8305. It is favorable that the display portion 8302 be curved. When the display portion 8302 is curved, a user can feel high realistic sensation of images. Although the structure described in this embodiment as an example has one display portion 8302, the number of the display portions 8302 provided is not limited to one. For example, two display portions 8302 may be provided, in which case one display portion is provided for one corresponding user's eye, so that three-dimensional display using parallax or the like is possible.

The display device of one embodiment of the present invention can be used in the display portion 8302. The display device including the semiconductor device of one embodiment of the present invention has an extremely high resolution; thus, even when an image is magnified using the lenses 8305 as illustrated in FIG. 38E, the user does not perceive pixels, and thus a more realistic image can be displayed.

<7-3. Electronic Device 2>

Next, FIGS. 39A to 39G illustrate examples of electronic devices that are different from those illustrated in FIGS. 38A to 38E.

Electronic devices illustrated in FIGS. 39A to 39G include a housing 9000, a display portion 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, gradient, oscillation, odor, or infrared ray), a microphone 9008, and the like.

The electronic devices in FIGS. 39A to 39G have a variety of functions such as a function of displaying a variety of information (e.g., a still image, a moving image, and a text image) on the display portion, a touch panel function, a function of displaying a calendar, date, time, and the like, a function of controlling processing with a variety of software (programs), a wireless communication function, a function of being connected to a variety of computer networks with a wireless communication function, a function of transmitting and receiving a variety of data with a wireless communication function, and a function of reading out a program or data stored in a recording medium and displaying it on the display portion. Note that functions of the electronic devices in FIGS. 39A to 39G are not limited thereto, and the electronic devices can have a variety of functions. Although not illustrated in FIGS. 39A to 39G, the electronic devices may each have a plurality of display portions. Furthermore, the electronic devices may each be provided with a camera and the like to have a function of taking a still image, a function of taking a moving image, a function of storing the taken image in a memory medium (an external memory medium or a memory medium incorporated in the camera), a function of displaying the taken image on the display portion, or the like.

The electronic devices in FIGS. 39A to 39G are described in detail below.

FIG. 39A is a perspective view illustrating a television device 9100. The television device 9100 can include the display portion 9001 having a large screen size of, for example, 50 inches or more, or 100 inches or more.

FIG. 39B is a perspective view of a portable information terminal 9101. The portable information terminal 9101 functions as, for example, one or more of a telephone set, a notebook, and an information browsing system. Specifically, the portable information terminal 9101 can be used as a smartphone. Note that the portable information terminal 9101 may include a speaker 9003, a connection terminal 9006, a sensor 9007, or the like. The portable information terminal 9101 can display text and image information on its plurality of surfaces. For example, three operation buttons 9050 (also referred to as operation icons or simply as icons) can be displayed on one surface of the display portion 9001. Furthermore, information 9051 indicated by dashed rectangles can be displayed on another surface of the display portion 9001. Examples of the information 9051 include display indicating reception of an e-mail, a social networking service (SNS) message, or a telephone call, the title and sender of an e-mail or an SNS message, date, time, remaining battery, and reception strength of an antenna. Alternatively, the operation buttons 9050 or the like may be displayed in place of the information 9051.

FIG. 39C is a perspective view of a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001. Here, information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user of the portable information terminal 9102 can see the display (here, the information 9053) on the portable information terminal 9102 put in a breast pocket of his/her clothes. Specifically, a caller's phone number, name, or the like of an incoming call is displayed in a position that can be seen from above the portable information terminal 9102. The user can see the display without taking out the portable information terminal 9102 from the pocket and decide whether to answer the call.

FIG. 39D is a perspective view of a watch-type portable information terminal 9200. The portable information terminal 9200 is capable of executing a variety of applications such as mobile phone calls, e-mailing, reading and editing texts, music reproduction, Internet communication, and a computer game. The display surface of the display portion 9001 is curved, and display can be performed on the curved display surface. The portable information terminal 9200 can employ near field communication conformable to a communication standard. For example, hands-free calling can be achieved by mutual communication between the portable information terminal 9200 and a headset capable of wireless communication. Moreover, the portable information terminal 9200 includes the connection terminal 9006 and can perform direct data communication with another information terminal via a connector. Charging through the connection terminal 9006 is also possible. Note that the charging operation may be performed by wireless power feeding without using the connection terminal 9006.

FIGS. 39E, 39F, and 39G are perspective views of a foldable portable information terminal 9201 that is opened, that is shifted from the opened state to the folded state or from the folded state to the opened state, and that is folded, respectively. The portable information terminal 9201 is highly portable when folded. When the portable information terminal 9201 is opened, a seamless large display region is highly browsable. The display portion 9001 of the portable information terminal 9201 is supported by three housings 9000 joined by hinges 9055. By being folded at the hinges 9055 between the two adjacent housings 9000, the portable information terminal 9201 can be reversibly changed in shape from the opened state to the folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature greater than or equal to 1 mm and less than or equal to 150 mm.

Next, an example of an electronic device that is different from the electronic devices illustrated in FIGS. 38A to 38E and FIGS. 39A to 39G is illustrated in FIGS. 40A and 40B. FIGS. 40A and 40B are perspective views of a display device including a plurality of display panels. Note that the plurality of display panels are wound in the perspective view in FIG. 40A, and are unwound in the perspective view in FIG. 40B.

A display device 9500 illustrated in FIGS. 40A and 40B includes a plurality of display panels 9501, a hinge 9511, and a bearing 9512. The plurality of display panels 9501 each include a display region 9502 and a light-transmitting region 9503.

Each of the plurality of display panels 9501 is flexible. Two adjacent display panels 9501 are provided so as to partly overlap with each other. For example, the light-transmitting regions 9503 of the two adjacent display panels 9501 can overlap with each other. A display device having a large screen can be obtained with the plurality of display panels 9501. The display device is highly versatile because the display panels 9501 can be wound depending on its use.

Although the display regions 9502 of the adjacent display panels 9501 are separated from each other in FIGS. 40A and 40B, without limitation to this structure, the display regions 9502 of the adjacent display panels 9501 may overlap with each other without any space so that a continuous display region 9502 is obtained, for example.

Electronic devices described in this embodiment are characterized by having a display portion for displaying some sort of information. Note that the semiconductor device of one embodiment of the present invention can also be used for an electronic device that does not have a display portion.

The structures described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

This application is based on Japanese Patent Application serial no. 2016-041734 filed with Japan Patent Office on Mar. 4, 2016 and Japanese Patent Application serial no. 2016-125924 filed with Japan Patent Office on Jun. 24, 2016, the entire contents of which are hereby incorporated by reference. 

What is claimed is:
 1. A semiconductor device comprising: a first gate electrode; a first insulating film over the first gate electrode; an oxide semiconductor film over the first insulating film; a source electrode over the oxide semiconductor film; a drain electrode over the oxide semiconductor film; a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode; and a second gate electrode over the second insulating film, wherein the source electrode and the drain electrode each include a first conductive film, a second conductive film over and in contact with the first conductive film, and a third conductive film over and in contact with the second conductive film, wherein the second conductive film includes copper, wherein the first conductive film and the third conductive film each include an oxide conductive film, wherein an end portion of the first conductive film is located outward from an end portion of the second conductive film, wherein the third conductive film covers a top surface and a side surface of the second conductive film and is in contact with the first conductive film, and wherein the third conductive film includes a stacked-layer structure of a metal film and the oxide conductive film.
 2. The semiconductor device according to claim 1, further comprising a pixel electrode over and in contact with the second insulating film, wherein an opening portion is included in the second insulating film, and wherein the pixel electrode is electrically connected to the third conductive film through the opening portion.
 3. The semiconductor device according to claim 2, wherein the pixel electrode and the second gate electrode each include a fourth conductive film and a fifth conductive film over the fourth conductive film.
 4. The semiconductor device according to claim 3, wherein the fourth conductive film includes an oxide conductive film.
 5. The semiconductor device according to claim 1, wherein the oxide semiconductor film includes In, M, and Zn, and wherein the M is Al, Ga, Y, or Sn.
 6. The semiconductor device according to claim 1, wherein the oxide semiconductor film includes a crystal part, and wherein the crystal part has c-axis alignment.
 7. A display device comprising the semiconductor device according to claim 1, wherein the display device comprises a display element.
 8. A display module comprising the display device according to claim 7, wherein the display module comprises a touch sensor.
 9. An electronic device comprising the semiconductor device according to claim 1, wherein the electronic device comprises at least one of an operation key and a battery.
 10. The semiconductor device according to claim 1, wherein the oxide conductive film comprises an oxide including indium and tin or an oxide including indium and zinc.
 11. A semiconductor device comprising: a first gate electrode; a first insulating film over the first gate electrode; a first oxide semiconductor film over the first insulating film; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode over the second oxide semiconductor film; a drain electrode over the second oxide semiconductor film; a second insulating film over the second oxide semiconductor film, the source electrode, and the drain electrode; and a second gate electrode over the second insulating film, wherein the source electrode and the drain electrode each include a first conductive film, a second conductive film over and in contact with the first conductive film, and a third conductive film over and in contact with the second conductive film, wherein the second conductive film includes copper, wherein the first conductive film and the third conductive film each include an oxide conductive film, wherein an end portion of the first conductive film is located outward from an end portion of the second conductive film, wherein the third conductive film covers a top surface and a side surface of the second conductive film and is in contact with the first conductive film, and wherein the third conductive film includes a stacked-layer structure of a metal film and the oxide conductive film.
 12. The semiconductor device according to claim 11, further comprising a pixel electrode over and in contact with the second insulating film, wherein an opening portion is included in the second insulating film, and wherein the pixel electrode is electrically connected to the third conductive film through the opening portion.
 13. The semiconductor device according to claim 11, wherein the first oxide semiconductor film and the second oxide semiconductor film each include In, M, and Zn, and wherein the M is Al, Ga, Y, or Sn.
 14. The semiconductor device according to claim 13, wherein an atomic proportion of In in the first oxide semiconductor film is larger than an atomic proportion of M in the first oxide semiconductor film.
 15. The semiconductor device according to claim 11, wherein the oxide conductive film comprises an oxide including indium and tin or an oxide including indium and zinc.
 16. The semiconductor device according to claim 12, wherein the pixel electrode and the second gate electrode each include a fourth conductive film and a fifth conductive film over the fourth conductive film.
 17. The semiconductor device according to claim 16, wherein the fourth conductive film includes an oxide conductive film. 